blob: 59fbbb7aeae61ec619a93cf6a739b20b0e2b0660 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
|
// Simulator for the RISC-V[ECTOR] mini-ISA
// Copyright (C) 2025 Siddarth Suresh
// Copyright (C) 2025 bdunahu
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
#include "controller.h"
#include "ex.h"
#include "response.h"
#include "storage.h"
Controller::Controller(Stage *stage, Storage *storage, bool is_pipelined)
: Stage(stage)
{
this->clock_cycle = 1;
this->storage = storage;
this->is_pipelined = is_pipelined;
this->is_empty = true;
this->pc = 0x0;
this->checked_out = {};
this->gprs = {0};
this->gprs.at(2) = MEM_WORDS; // set the stack pointer
// grant side-door access
this->id = SIDE;
}
void Controller::run_for(int number)
{
int i;
for (i = 0; i < number; ++i) {
try {
this->advance(WAIT);
} catch (HaltException &e) {
break;
}
}
}
int Controller::get_clock_cycle() { return this->clock_cycle; }
std::array<int, GPR_NUM> Controller::get_gprs() { return this->gprs; }
int Controller::get_pc() { return this->pc; }
InstrDTO *Controller::advance(Response p)
{
InstrDTO *r;
r = this->next->advance(p);
++this->clock_cycle;
if (r)
this->is_empty = true;
return r;
}
void Controller::advance_helper()
{
// TODO: check halt condition and call UI to refresh
}
|
