Add initial vector tests

6 files changed, 102 insertions, 3 deletions

diff --git a/input/adjacent-adder-vector.asm b/input/adjacent-adder-vector.asm
new file mode 100644
index 0000000..80bc8a3
--- /dev/null
+++ b/input/adjacent-adder-vector.asm
@@ -0,0 +1,18 @@
+;;;;;;;;
+;;; adds adjacent elements of a 4-element vector together,
+;;; storing the result in place. Uses the vector type.
+
+.data
+	arr 1 2 3 4
+	s 3
+.text
+	load $4 s($0) 	; set the vector-length register
+	addi $5 $0 arr
+	loadv $16 0($5)
+	addi $5 $5 0x1
+	loadv $17 0($6)
+	addv $16 $16 $17
+	storev $16 arr($0)
+	nop
+	nop
+	nop
diff --git a/input/exchange-sort.asm b/input/exchange-sort.asm
index de50608..d894e97 100644
--- a/input/exchange-sort.asm
+++ b/input/exchange-sort.asm
@@ -32,13 +32,13 @@ SWAPPER:
 	store $8 arr($6)
 
 EXIT:
-	addi $2 $5 0x0		;function postamble
+	addi $2 $5 0x0		; function postamble
 	pop $5
 	ret
 
 
 MAIN:
-	push $5			;function preamble
+	push $5			; function preamble
 	addi $5 $2 0x0
 	subi $2 $2 0x4
 
diff --git a/input/hard-matrices.asm b/input/hard-matrices.asm
index bcd8fa1..1659574 100644
--- a/input/hard-matrices.asm
+++ b/input/hard-matrices.asm
@@ -1,5 +1,5 @@
 ;;;;;;;;
-;;; performs a matrix multiply the matrices m1 and m2: 36 * 18, 18 * 100
+;;; performs a matrix multiply the matrices m1 and m2: 100 * 18, 18 * 36
 ;;;
 ;;; YES I VERIFIED THIS IS CORRECT
 ;;;
diff --git a/input/over_or_under.asm b/input/over_or_under.asm
new file mode 100644
index 0000000..4be18ab
--- /dev/null
+++ b/input/over_or_under.asm
@@ -0,0 +1,57 @@
+;;;;;;;;
+;;; tests the over/underflow conditions on various operations
+
+.data
+	n1 -1
+	space1 0 0 0 0 0 0 0 	; space is added to load this as a vector
+	max 0x7FFFFFFF
+	space2 0 0 0 0 0 0 0
+	min 0x80000000
+	vSiz 8
+
+.text
+	load $4 vSiz($0)
+	load $5 max($0)
+	load $6 min($0)
+	loadv $17 max($0)
+	loadv $18 min($0)
+	loadv $19 n1($0)
+	addi $7 $0 1
+	addi $8 $0 -1
+	jrl ADDROVER
+
+WIN:
+	nop
+	nop
+	nop
+	quot $0 $0 $0
+
+ADDROVER:
+	add $0 $5 $7
+	bof SUBRUNDER
+	jrl DIE
+
+SUBRUNDER:
+	sub $0 $6 $7
+	buf MULROK
+	jrl DIE
+
+MULROK:
+	mul $0 $5 $7
+	buf DIE
+	jrl MULVROVER
+
+MULVROVER:
+	mulv $16 $18 $19
+	bof DIVVIOVER
+	jrl DIE
+
+DIVVIOVER:
+	divv $15 $18 $19
+	bof WIN
+	jrl DIE
+
+DIE:
+	nop
+	nop
+	nop
diff --git a/input/rabbits.asm b/input/rabbits.asm
index 1f65549..f296cd2 100644
--- a/input/rabbits.asm
+++ b/input/rabbits.asm
@@ -18,3 +18,4 @@ DONE:
 	nop
 	nop
 	nop
+	div $0 $0 $0
diff --git a/input/vector_fun.asm b/input/vector_fun.asm
new file mode 100644
index 0000000..eed38ce
--- /dev/null
+++ b/input/vector_fun.asm
@@ -0,0 +1,23 @@
+;;;;;;;;
+;;; tests the ALU vector extension
+
+.data
+	s 4
+.text
+	load $4 s($0) 		; set the vector length register
+
+LOOP:
+	cev $17 $16
+	beq END
+
+	addv $17 $16 $17
+	addv $17 $16 $17
+	mulv $17 $17 $17
+	subv $17 $17 $16
+	subv $17 $17 $16
+	subv $17 $17 $16
+	jrl LOOP
+END:
+	nop
+	nop
+	nop