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| author | Siddarth Suresh <155843085+SiddarthSuresh98@users.noreply.github.com> | 2025-04-12 13:06:51 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-12 13:06:51 -0400 |
| commit | fc20e7e7276b712f1e8db773b9215f900e877169 (patch) | |
| tree | caecdd1499d2e391cd5bd2dcde3aebfade002a09 /rva.asd | |
| parent | 5dbf0b63988b42c112ca0087cbbbb090566df5c1 (diff) | |
| parent | 639098b1ea82be82bd18a4af415458fcbaf5e20b (diff) | |
Merge pull request #8 from bdunahu/bdunahu
Add write raw bytes stage
Diffstat (limited to 'rva.asd')
| -rw-r--r-- | rva.asd | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -4,7 +4,7 @@ (asdf:defsystem #:rva ;; :author "" ;; :license "" - :version "0.3" + :version "1.0" :homepage "https://github.com/bdunahu/rva" :description "Assembler for the RISC-V[ECTOR] mini-ISA." :source-control (:git "git@github.com:bdunahu/rva.git") |