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| -rw-r--r-- | README.md | 32 | ||||
| -rw-r--r-- | rva.asd | 5 |
2 files changed, 28 insertions, 9 deletions
@@ -1,12 +1,30 @@ -# RISC V[ECTOR] Assembler +# rva + + _/_/ _/_/ + _/ _/ + _/ _/ _/_/ _/ _/ _/_/_/ _/ + _/ _/_/ _/ _/ _/ _/ _/ + _/ _/ _/ _/ _/ _/ _/ + _/ _/ _/ _/_/_/ _/ + _/_/ _/_/ + +This is an assembler for the custom ISA nicknamed "RISC V[ECTOR]". It takes in an assembly program syntactically similar to MIPS (see input) and outputs a list of binary numbers corresponding to the instructions. This the output is compatible with the [RISC V[ECTOR]](https://github.com/bdunahu/RISC-V-ECTOR-) simulator. ## Dependencies -- SBCL -- ASDF -- fiveam -- clingon +A common-lisp implementation (SBCL) and the following libraries are required to compile: + +- SBCL (tested with v2.5.2) +- ASDF (tested with v3.3.7) +- fiveam (tested with v3.3.7) +- clingon (tested with v0.5.0-1.f2a730f) +- trivia (tested with v0.1-0.8b406c3) + +## To run + +Run `make` to produce a binary file in `/bin/`. To run the unit tests, run `make test`. See the make file for further options. -## To compile +# About -make +Created at the University of Massachusetts, Amherst +CS535 -- Computer Architecture and ISA Design
\ No newline at end of file @@ -4,12 +4,13 @@ (asdf:defsystem #:rva ;; :author "" ;; :license "" - :version "0.1" + :version "0.3" :homepage "https://github.com/bdunahu/rva" :description "Assembler for the RISC-V[ECTOR] mini-ISA." :source-control (:git "git@github.com:bdunahu/rva.git") :depends-on (:uiop - :clingon) + :clingon + :trivia) :components ((:module "src" :serial t :components ((:file "package") |