Merge pull request #26 from bdunahu/bdunahu

clarify macro names, implement load in CLI, fix many display issues

8 files changed, 87 insertions, 69 deletions

diff --git a/inc/cache.h b/inc/cache.h
index 17abcdd..31602ca 100644
--- a/inc/cache.h
+++ b/inc/cache.h
@@ -38,7 +38,7 @@ class Cache : public Storage
 	 * TODO this doesn't seem like good object-oriented practice.
 	 * @return this->meta
 	 */
-	std::array<std::array<int, 2>, L1_CACHE_SIZE> get_meta() const;
+	std::array<std::array<int, 2>, L1_CACHE_LINES> get_meta() const;
 
   private:
 	/**
@@ -54,7 +54,7 @@ class Cache : public Storage
 	 * element in `data` is invalid. If the most second value of an element
 	 * is nonzero, the corresponding element in `data` is dirty.
 	 */
-	std::array<std::array<int, 2>, L1_CACHE_SIZE> meta;
+	std::array<std::array<int, 2>, L1_CACHE_LINES> meta;
 };
 
 std::ostream &operator<<(std::ostream &os, const Cache &c);
diff --git a/inc/definitions.h b/inc/definitions.h
index f015ce9..eced554 100644
--- a/inc/definitions.h
+++ b/inc/definitions.h
@@ -13,33 +13,33 @@
 #define LINE_SIZE static_cast<int>(pow(2, 2))
 
 /**
+ * The number of bits to specify a memory word
  * The number of bits to specify a memory line
- * calculated as: (/ (expt 2 15) 4)
+ * The total number of lines in memory
  */
-#define MEM_SPEC 8
-/**
- * The total number of words in memory
- */
-#define MEM_SIZE static_cast<int>(pow(2, MEM_SPEC))
+#define MEM_WORD_SPEC 10
+#define MEM_LINE_SPEC static_cast<unsigned int>(MEM_WORD_SPEC - LINE_SPEC)
+#define MEM_WORDS static_cast<int>(pow(2, MEM_WORD_SPEC))
+#define MEM_LINES static_cast<int>(pow(2, MEM_LINE_SPEC))
 
 /**
+ * The number of bits to specify a l1 cache word
  * The number of bits to specify a l1 cache line
+ * The total number of lines in l1 cache
  */
-#define L1_CACHE_SPEC 5
-/**
- * The total number of words in l1 cache
- */
-#define L1_CACHE_SIZE static_cast<int>(pow(2, L1_CACHE_SPEC))
+#define L1_CACHE_WORD_SPEC 7
+#define L1_CACHE_LINE_SPEC static_cast<unsigned int>(L1_CACHE_WORD_SPEC - LINE_SPEC)
+#define L1_CACHE_LINES static_cast<int>(pow(2, L1_CACHE_LINE_SPEC))
 
 /**
  * The total number of cycles a memory access takes.
  */
-#define MEM_DELAY 4
+#define MEM_DELAY 3
 
 /**
  * The total number of cycles a level one cache access takes
  */
-#define L1_CACHE_DELAY 1
+#define L1_CACHE_DELAY 0
 
 /**
  * Return the N least-significant bits from integer K using a bit mask
diff --git a/src/cli/cli.cc b/src/cli/cli.cc
index a885aee..41ac57c 100644
--- a/src/cli/cli.cc
+++ b/src/cli/cli.cc
@@ -100,14 +100,15 @@ void Cli::help()
 
 void Cli::load(Accessor accessor, int address)
 {
+	address = wrap_address(address);
 	const auto default_flags = std::cout.flags();
 	const auto default_fill = std::cout.fill();
 
 	signed int data;
-	// Response r = this->cache->read_word(accessor, address, data);
-	// std::cout << r << " to " << accessor << " reading " << address << std::endl;
-	// if (r == OK)
-	// 	std::cout << "\tGot:" << std::hex << data;
+	Response r = this->cache->read_word(accessor, address, data);
+	std::cout << r << " to " << accessor << " reading " << address << std::endl;
+	if (r == OK)
+		std::cout << "  Got: " << std::hex << data << std::endl;
 
 	std::cout.flags(default_flags);
 	std::cout.fill(default_fill);
@@ -115,8 +116,9 @@ void Cli::load(Accessor accessor, int address)
 
 void Cli::store(Accessor accessor, int data, int address)
 {
+	address = wrap_address(address);
 	Response r = this->cache->write_word(accessor, data, address);
-	std::cout << r << " to " << accessor << " storing " << data << " in"
+	std::cout << r << " to " << accessor << " storing " << data << " in "
 			  << address << std::endl;
 }
 
@@ -209,7 +211,7 @@ void Cli::initialize()
 	if (this->cache != nullptr)
 		delete this->cache;
 
-	Dram *d = new Dram(MEM_SIZE, MEM_DELAY);
+	Dram *d = new Dram(MEM_LINES, MEM_DELAY);
 	this->cache = new Cache(d, L1_CACHE_DELAY);
 	this->cycle = 1;
 }
diff --git a/src/storage/cache.cc b/src/storage/cache.cc
index 533d0ec..3e2a5e0 100644
--- a/src/storage/cache.cc
+++ b/src/storage/cache.cc
@@ -10,7 +10,7 @@
 Cache::Cache(Storage *lower, int delay)
 {
 	this->data = new std::vector<std::array<signed int, LINE_SIZE>>;
-	this->data->resize(L1_CACHE_SIZE);
+	this->data->resize(L1_CACHE_LINES);
 	this->delay = delay;
 	this->is_waiting = false;
 	this->lower = lower;
@@ -119,29 +119,31 @@ Response Cache::read_word(Accessor accessor, int address, signed int &data)
 void Cache::fetch_resource(int expected)
 {
 	Response r = OK;
+	Response q;
 	int tag, index, offset;
-	std::array<signed int, LINE_SIZE> actual;
+	std::array<signed int, LINE_SIZE> *actual;
 	std::array<int, 2> *meta;
 
 	get_bit_fields(expected, &tag, &index, &offset);
 	meta = &this->meta.at(index);
-	actual = this->data->at(index);
+	actual = &this->data->at(index);
 
 	if (meta->at(0) != tag) {
+		r = WAIT;
 		// address not in cache
 		if (meta->at(1) >= 0) {
 			// occupant is dirty
 			// writing line to DRam in case of dirty cache eviction
-			r = this->lower->write_line(
-				L1CACHE, actual,
+			q = this->lower->write_line(
+				L1CACHE, *actual,
 				((index << LINE_SPEC) +
-				 (meta->at(0) << (L1_CACHE_SPEC + LINE_SPEC))));
-			if (r == OK) {
+				 (meta->at(0) << (L1_CACHE_LINE_SPEC + LINE_SPEC))));
+			if (q == OK) {
 				meta->at(1) = -1;
 			}
 		} else {
-			r = this->lower->read_line(L1CACHE, expected, actual);
-			if (r == OK) {
+			q = this->lower->read_line(L1CACHE, expected, *actual);
+			if (q == OK) {
 				meta->at(0) = tag;
 			}
 		}
@@ -150,9 +152,9 @@ void Cache::fetch_resource(int expected)
 	this->is_waiting = (r == OK) ? false : true;
 }
 
-std::array<std::array<int, 2>, L1_CACHE_SIZE> Cache::get_meta() const
+std::array<std::array<int, 2>, L1_CACHE_LINES> Cache::get_meta() const
 {
-	std::array<std::array<int, 2>, L1_CACHE_SIZE> ret;
+	std::array<std::array<int, 2>, L1_CACHE_LINES> ret;
 	std::copy(std::begin(this->meta), std::end(this->meta), std::begin(ret));
 	return ret;
 }
@@ -163,24 +165,32 @@ std::ostream &operator<<(std::ostream &os, const Cache &c)
 	const auto default_fill = std::cout.fill();
 
 	std::vector<std::array<signed int, LINE_SIZE>> data =
-		c.view(0, L1_CACHE_SIZE);
-	std::array<std::array<int, 2>, L1_CACHE_SIZE> meta = c.get_meta();
+		c.view(0, L1_CACHE_LINES);
+	std::array<std::array<int, 2>, L1_CACHE_LINES> meta = c.get_meta();
 
-	os << " " << std::setfill(' ') << std::setw(L1_CACHE_SPEC + 2) << "INDEX"
+	os << " " << std::setfill(' ') << std::setw(L1_CACHE_LINE_SPEC + 2)
+	   << "INDEX"
 	   << " | " << std::setfill(' ') << std::setw((8 + 3) * 4 - 1) << "DATA"
 	   << " | " << std::setfill(' ')
-	   << std::setw(MEM_SPEC - LINE_SPEC - L1_CACHE_SPEC + 2) << "TAG"
+	   << std::setw(MEM_LINE_SPEC - L1_CACHE_LINE_SPEC + 2) << "TAG"
 	   << " | D" << std::endl;
-	for (int i = 0; i < L1_CACHE_SIZE; ++i) {
-		os << " 0b" << std::setw(L1_CACHE_SPEC) << std::bitset<L1_CACHE_SPEC>(i)
-		   << " | ";
+	for (int i = 0; i < L1_CACHE_LINES; ++i) {
+		os << " 0b" << std::setw(L1_CACHE_LINE_SPEC)
+		   << std::bitset<L1_CACHE_LINE_SPEC>(i) << " | ";
 		for (int j = 0; j < LINE_SIZE; ++j) {
 			os << "0x" << std::setfill('0') << std::setw(8) << std::hex
 			   << data.at(i).at(j) << " ";
 		}
-		os << "| 0x" << std::setfill(' ')
-		   << std::bitset<MEM_SPEC - LINE_SPEC - L1_CACHE_SPEC>(meta.at(i)[0])
-		   << " | " << (int)(meta.at(i)[0] >= 0) << std::endl;
+		os << "| 0b" << std::setfill(' ');
+
+		if (meta.at(i)[0] < 0)
+			os << std::setfill('?')
+			   << std::setw(MEM_LINE_SPEC - L1_CACHE_LINE_SPEC) << "";
+		else
+			os << std::bitset<MEM_LINE_SPEC - L1_CACHE_LINE_SPEC>(
+				meta.at(i)[0]);
+
+		os << " | " << (int)(meta.at(i)[0] >= 0) << std::endl;
 	}
 
 	std::cout.flags(default_flags);
diff --git a/src/storage/dram.cc b/src/storage/dram.cc
index f375a76..56eec47 100644
--- a/src/storage/dram.cc
+++ b/src/storage/dram.cc
@@ -6,6 +6,7 @@
 #include <bitset>
 #include <iostream>
 #include <iterator>
+#include <utils.h>
 
 Dram::Dram(int lines, int delay)
 {
@@ -22,6 +23,7 @@ Dram::~Dram() { delete this->data; }
 
 void Dram::do_write(signed int data, int address)
 {
+	address = wrap_address(address);
 	int line = address / LINE_SIZE;
 	int word = address % LINE_SIZE;
 
@@ -31,18 +33,21 @@ void Dram::do_write(signed int data, int address)
 void Dram::do_write_line(
 	std::array<signed int, LINE_SIZE> data_line, int address)
 {
+	address = wrap_address(address);
 	int line = address / LINE_SIZE;
 	this->data->at(line) = data_line;
 }
 
 void Dram::do_read(std::array<signed int, LINE_SIZE> &data_line, int address)
 {
+	address = wrap_address(address);
 	int line = address / LINE_SIZE;
 	data_line = this->data->at(line);
 }
 
 void Dram::do_read_word(signed int &data, int address)
 {
+	address = wrap_address(address);
 	int line = address / LINE_SIZE;
 	int word = address % LINE_SIZE;
 	data = this->data->at(line).at(word);
@@ -136,13 +141,15 @@ std::ostream &operator<<(std::ostream &os, const Dram &d)
 	const auto default_flags = std::cout.flags();
 	const auto default_fill = std::cout.fill();
 
-	std::vector<std::array<signed int, LINE_SIZE>> data = d.view(0, MEM_SIZE);
+	std::vector<std::array<signed int, LINE_SIZE>> data = d.view(0, MEM_LINES);
 
-	os << " " << std::setfill(' ') << std::setw(MEM_SPEC + 2) << "INDEX"
+	os << " " << std::setfill(' ') << std::setw(MEM_LINE_SPEC + 2 + LINE_SPEC)
+	   << "ADDRESS"
 	   << " | " << std::setfill(' ') << std::setw((8 + 3) * 4 - 1) << "DATA"
 	   << std::endl;
-	for (int i = 0; i < MEM_SIZE; ++i) {
-		os << " 0b" << std::setw(MEM_SPEC) << std::bitset<MEM_SPEC>(i) << " | ";
+	for (int i = 0; i < MEM_LINES; ++i) {
+		os << " 0b" << std::setw(MEM_LINE_SPEC + LINE_SPEC) << left
+		   << std::bitset<MEM_LINE_SPEC>(i) << " | ";
 		for (int j = 0; j < LINE_SIZE; ++j) {
 			os << "0x" << std::setfill('0') << std::setw(8) << std::hex
 			   << data.at(i).at(j) << ' ';
diff --git a/src/utils/utils.cc b/src/utils/utils.cc
index f95d88f..ebbc1e9 100644
--- a/src/utils/utils.cc
+++ b/src/utils/utils.cc
@@ -7,9 +7,8 @@
 void get_bit_fields(int address, int *tag, int *index, int *offset)
 {
 	*tag = GET_MID_BITS(
-		address, LINE_SPEC + L1_CACHE_SPEC,
-		MEM_SPEC + LINE_SPEC + L1_CACHE_SPEC);
-	*index = GET_MID_BITS(address, LINE_SPEC, L1_CACHE_SPEC + LINE_SPEC);
+		address, L1_CACHE_LINE_SPEC + LINE_SPEC, MEM_WORD_SPEC);
+	*index = GET_MID_BITS(address, LINE_SPEC, L1_CACHE_LINE_SPEC + LINE_SPEC);
 	*offset = GET_LS_BITS(address, LINE_SPEC);
 }
 
@@ -31,7 +30,7 @@ const std::string string_format(const char *const zcFormat, ...)
 
 int wrap_address(int address) {
 	if (address < 0){
-		return ((address % MEM_SIZE) + MEM_SIZE) % MEM_SIZE;
+		return ((address % MEM_WORDS) + MEM_WORDS) % MEM_WORDS;
 	}
-	return address % MEM_SIZE;
+	return address % MEM_WORDS;
 }
diff --git a/tests/cache.cc b/tests/cache.cc
index d7b3444..daaec90 100644
--- a/tests/cache.cc
+++ b/tests/cache.cc
@@ -15,7 +15,7 @@ TEST_CASE("Constructor singleton cache", "[cache]")
 TEST_CASE("no delay stores instantly", "[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_SIZE, delay);
+	Dram *d = new Dram(MEM_LINES, delay);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -43,7 +43,7 @@ TEST_CASE("no delay stores instantly", "[cache]")
 TEST_CASE("cache takes \"forever\"", "[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_SIZE, delay);
+	Dram *d = new Dram(MEM_LINES, delay);
 	Cache *c = new Cache(d, delay + 2);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -79,7 +79,7 @@ TEST_CASE("cache takes \"forever\"", "[cache]")
 TEST_CASE("dram takes \"forever\"", "[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_SIZE, delay + 2);
+	Dram *d = new Dram(MEM_LINES, delay + 2);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -115,7 +115,7 @@ TEST_CASE("dram takes \"forever\"", "[cache]")
 TEST_CASE("dram and cache take \"forever\"", "[cache]")
 {
 	int delay = 2;
-	Dram *d = new Dram(MEM_SIZE, delay + 2);
+	Dram *d = new Dram(MEM_LINES, delay + 2);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -162,7 +162,7 @@ TEST_CASE(
 	"dram takes \"forever\", two concurrent requests same index", "[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_SIZE, delay + 2);
+	Dram *d = new Dram(MEM_LINES, delay + 2);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
@@ -217,7 +217,7 @@ TEST_CASE(
 	"[cache]")
 {
 	int delay = 0;
-	Dram *d = new Dram(MEM_SIZE, delay + 2);
+	Dram *d = new Dram(MEM_LINES, delay + 2);
 	Cache *c = new Cache(d, delay);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
 	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
diff --git a/tests/utils.cc b/tests/utils.cc
index f0e4c24..ea1a1ed 100644
--- a/tests/utils.cc
+++ b/tests/utils.cc
@@ -5,9 +5,9 @@
 TEST_CASE("Parse arbitrary fields # one", "[cache]")
 {
 	int tag, index, offset;
-	int address = 0b111110001010101;
+	int address = 0b0001010101;
 	get_bit_fields(address, &tag, &index, &offset);
-	CHECK(tag == 0b11111000);
+	CHECK(tag == 0b000);
 	CHECK(index == 0b10101);
 	CHECK(offset == 0b01);
 }
@@ -15,30 +15,30 @@ TEST_CASE("Parse arbitrary fields # one", "[cache]")
 TEST_CASE("Parse arbitrary fields # two", "[cache]")
 {
 	int tag, index, offset;
-	int address = 0b000110100111011;
+	int address = 0b0100111011;
 	get_bit_fields(address, &tag, &index, &offset);
-	CHECK(tag == 0b00011010);
+	CHECK(tag == 0b010);
 	CHECK(index == 0b01110);
 	CHECK(offset == 0b11);
 }
 
 TEST_CASE("wrap address outside upper bound", "[utils]")
 {
-	int address = MEM_SIZE + 25;
+	int address = MEM_WORDS + 25;
 	int wrapped = wrap_address(address);
 	REQUIRE(wrapped == 25);
 }
 
 TEST_CASE("wrap address inside upper bound", "[utils]")
 {
-	int address = MEM_SIZE - 25;
+	int address = MEM_WORDS - 25;
 	int wrapped = wrap_address(address);
-	REQUIRE(wrapped == MEM_SIZE - 25);
+	REQUIRE(wrapped == MEM_WORDS - 25);
 }
 
 TEST_CASE("wrap address at upper bound", "[utils]")
 {
-	int address = MEM_SIZE;
+	int address = MEM_WORDS;
 	int wrapped = wrap_address(address);
 	REQUIRE(wrapped == 0);
 }
@@ -47,14 +47,14 @@ TEST_CASE("wrap address lower than 0 with magnitude lesser than mem size", "[uti
 {
 	int address = -10;
 	int wrapped = wrap_address(address);
-	REQUIRE(wrapped == MEM_SIZE - 10);
+	REQUIRE(wrapped == MEM_WORDS - 10);
 }
 
 TEST_CASE("wrap address lower than 0 but with magnitude greater than mem size", "[utils]")
 {
-	int address = -(MEM_SIZE + 10);
+	int address = -(MEM_WORDS + 10);
 	int wrapped = wrap_address(address);
-	REQUIRE(wrapped == MEM_SIZE - 10);
+	REQUIRE(wrapped == MEM_WORDS - 10);
 }
 
 TEST_CASE("wrap address at 0", "[utils]")
@@ -62,4 +62,4 @@ TEST_CASE("wrap address at 0", "[utils]")
 	int address = 0;
 	int wrapped = wrap_address(address);
 	REQUIRE(wrapped == 0);
-}
\ No newline at end of file
+}