Merge pull request #25 from bdunahu/dev-sid

support for read word, write line in all levels of storage, cache load, dirty cache eviction, memory address wrapping

11 files changed, 673 insertions, 99 deletions

diff --git a/inc/cache.h b/inc/cache.h
index 04f6181..17abcdd 100644
--- a/inc/cache.h
+++ b/inc/cache.h
@@ -20,11 +20,18 @@ class Cache : public Storage
 	Cache(Storage *lower, int delay);
 	~Cache();
 
-	Response write(Accessor accessor, signed int data, int address) override;
-	Response read(
+	Response
+	write_word(Accessor accessor, signed int data, int address) override;
+	Response write_line(
+		Accessor accessor,
+		std::array<signed int, LINE_SIZE> data_line,
+		int address) override;
+	Response read_line(
 		Accessor accessor,
 		int address,
-		std::array<signed int, LINE_SIZE> &data) override;
+		std::array<signed int, LINE_SIZE> &data_line) override;
+	Response
+	read_word(Accessor accessor, int address, signed int &data) override;
 
 	/**
 	 * Getter for the meta attribute.
diff --git a/inc/dram.h b/inc/dram.h
index 2d4088f..2771c3e 100644
--- a/inc/dram.h
+++ b/inc/dram.h
@@ -17,21 +17,37 @@ class Dram : public Storage
 	Dram(int lines, int delay);
 	~Dram();
 
-	Response write(Accessor accessor, signed int data, int address) override;
-	Response read(
+	Response
+	write_word(Accessor accessor, signed int data, int address) override;
+	Response read_line(
 		Accessor accessor,
 		int address,
-		std::array<signed int, LINE_SIZE> &data) override;
+		std::array<signed int, LINE_SIZE> &data_line) override;
+	Response write_line(
+		Accessor accessor,
+		std::array<signed int, LINE_SIZE> data_line,
+		int address) override;
+	Response
+	read_word(Accessor accessor, int address, signed int &data) override;
 
   private:
 	/**
-	 * Helper for `write`.
+	 * Helper for `write` a word
 	 */
 	void do_write(signed int, int);
 	/**
-	 * Helper for `read`.
+	 * Helper for writing a line.
+	 */
+	void
+	do_write_line(std::array<signed int, LINE_SIZE> data_line, int address);
+	/**
+	 * Helper for `read` a line
 	 */
 	void do_read(std::array<signed int, LINE_SIZE> &data_line, int address);
+	/**
+	 * Helper for reading a word.
+	 */
+	void do_read_word(signed int &data, int address);
 };
 
 std::ostream &operator<<(std::ostream &os, const Dram &d);
diff --git a/inc/storage.h b/inc/storage.h
index a30e74d..b54a6f7 100644
--- a/inc/storage.h
+++ b/inc/storage.h
@@ -14,24 +14,37 @@ class Storage
 	virtual ~Storage() = default;
 
 	/**
-	 * Write `data` into `address`.
+	 * Write `data` word into `address`.
 	 * @param the source making the request.
 	 * @param the data (hexadecimal) to write.
 	 * @param the address to write to.
 	 * @return a status code reflecting the state of the request.
 	 */
-	virtual Response write(Accessor accessor, signed int data, int address) = 0;
+	virtual Response write_word(Accessor accessor, signed int data, int address) = 0;
+
+	/**
+	 * Write a data line to given address in this level of storage
+	 */
+	virtual Response write_line(Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address) = 0;
+
+	
 	/**
-	 * Get the data at `address`.
+	 * Get the data line at `address`.
 	 * @param the source making the request.
 	 * @param the address being accessed.
 	 * @return a status code reflecting the state of the request, and the
 	 * data being returned.
 	 */
-	virtual Response read(
+	virtual Response read_line(
 		Accessor accessor,
 		int address,
 		std::array<signed int, LINE_SIZE> &data) = 0;
+
+	/**
+	 * Read a word from given address in this level of storage
+	 */
+	virtual Response read_word(Accessor accessor, int address, signed int &data) = 0;
+	
 	/**
 	 * Sidedoor view of `lines` of memory starting at `base`.
 	 * @param The base line to start getting memory from.
diff --git a/inc/utils.h b/inc/utils.h
index 71e515b..aa8831b 100644
--- a/inc/utils.h
+++ b/inc/utils.h
@@ -20,4 +20,6 @@ void get_bit_fields(int address, int *tag, int *index, int *offset);
  */
 const std::string string_format(const char *const zcFormat, ...);
 
+int wrap_address(int address);
+
 #endif /* UTILS_H_INCLUDED */
diff --git a/src/cli/cli.cc b/src/cli/cli.cc
index 0729e00..a885aee 100644
--- a/src/cli/cli.cc
+++ b/src/cli/cli.cc
@@ -115,7 +115,7 @@ void Cli::load(Accessor accessor, int address)
 
 void Cli::store(Accessor accessor, int data, int address)
 {
-	Response r = this->cache->write(accessor, data, address);
+	Response r = this->cache->write_word(accessor, data, address);
 	std::cout << r << " to " << accessor << " storing " << data << " in"
 			  << address << std::endl;
 }
diff --git a/src/storage/cache.cc b/src/storage/cache.cc
index 1a8a10b..533d0ec 100644
--- a/src/storage/cache.cc
+++ b/src/storage/cache.cc
@@ -25,7 +25,7 @@ Cache::~Cache()
 	delete this->data;
 }
 
-Response Cache::write(Accessor accessor, signed int data, int address)
+Response Cache::write_word(Accessor accessor, signed int data, int address)
 {
 	Response r = WAIT;
 
@@ -49,10 +49,71 @@ Response Cache::write(Accessor accessor, signed int data, int address)
 	return r;
 }
 
-Response Cache::read(
-	Accessor accessor, int address, std::array<signed int, LINE_SIZE> &data)
+Response Cache::write_line(
+	Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address)
 {
-	return WAIT;
+	Response r = WAIT;
+
+	/* Do this first--then process the first cycle immediately. */
+	if (this->requester == IDLE)
+		this->requester = accessor;
+
+	if (this->requester == accessor) {
+		fetch_resource(address);
+		if (this->is_waiting)
+			r = BLOCKED;
+		else if (this->wait_time == 0) {
+			int tag, index, offset;
+			get_bit_fields(address, &tag, &index, &offset);
+			this->data->at(index) = data_line;
+			this->meta[index].at(1) = 1;
+			r = OK;
+		}
+	}
+
+	return r;
+}
+
+// TODO: tests for multi level cache
+Response Cache::read_line(
+	Accessor accessor,
+	int address,
+	std::array<signed int, LINE_SIZE> &data_line)
+{
+	Response r = WAIT;
+	if (this->requester == IDLE)
+		this->requester = accessor;
+	if (this->requester == accessor) {
+		fetch_resource(address);
+		if (this->is_waiting)
+			r = BLOCKED;
+		else if (this->wait_time == 0) {
+			int tag, index, offset;
+			get_bit_fields(address, &tag, &index, &offset);
+			data_line = this->data->at(index);
+			r = OK;
+		}
+	}
+	return r;
+}
+
+Response Cache::read_word(Accessor accessor, int address, signed int &data)
+{
+	Response r = WAIT;
+	if (this->requester == IDLE)
+		this->requester = accessor;
+	if (this->requester == accessor) {
+		fetch_resource(address);
+		if (this->is_waiting)
+			r = BLOCKED;
+		else if (this->wait_time == 0) {
+			int tag, index, offset;
+			get_bit_fields(address, &tag, &index, &offset);
+			data = this->data->at(index).at(offset);
+			r = OK;
+		}
+	}
+	return r;
 }
 
 void Cache::fetch_resource(int expected)
@@ -64,19 +125,24 @@ void Cache::fetch_resource(int expected)
 
 	get_bit_fields(expected, &tag, &index, &offset);
 	meta = &this->meta.at(index);
+	actual = this->data->at(index);
 
 	if (meta->at(0) != tag) {
 		// address not in cache
 		if (meta->at(1) >= 0) {
 			// occupant is dirty
-			// TODO
-			r = WAIT;
+			// writing line to DRam in case of dirty cache eviction
+			r = this->lower->write_line(
+				L1CACHE, actual,
+				((index << LINE_SPEC) +
+				 (meta->at(0) << (L1_CACHE_SPEC + LINE_SPEC))));
+			if (r == OK) {
+				meta->at(1) = -1;
+			}
 		} else {
-			actual = this->data->at(index);
-			r = this->lower->read(L1CACHE, expected, actual);
+			r = this->lower->read_line(L1CACHE, expected, actual);
 			if (r == OK) {
 				meta->at(0) = tag;
-				meta->at(1) = -1;
 			}
 		}
 	}
diff --git a/src/storage/dram.cc b/src/storage/dram.cc
index e755c2a..f375a76 100644
--- a/src/storage/dram.cc
+++ b/src/storage/dram.cc
@@ -20,7 +20,7 @@ Dram::Dram(int lines, int delay)
 
 Dram::~Dram() { delete this->data; }
 
-void Dram::do_write(signed data, int address)
+void Dram::do_write(signed int data, int address)
 {
 	int line = address / LINE_SIZE;
 	int word = address % LINE_SIZE;
@@ -28,7 +28,50 @@ void Dram::do_write(signed data, int address)
 	this->data->at(line).at(word) = data;
 }
 
-Response Dram::write(Accessor accessor, signed int data, int address)
+void Dram::do_write_line(
+	std::array<signed int, LINE_SIZE> data_line, int address)
+{
+	int line = address / LINE_SIZE;
+	this->data->at(line) = data_line;
+}
+
+void Dram::do_read(std::array<signed int, LINE_SIZE> &data_line, int address)
+{
+	int line = address / LINE_SIZE;
+	data_line = this->data->at(line);
+}
+
+void Dram::do_read_word(signed int &data, int address)
+{
+	int line = address / LINE_SIZE;
+	int word = address % LINE_SIZE;
+	data = this->data->at(line).at(word);
+}
+
+Response Dram::write_line(
+	Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address)
+{
+	Response r = WAIT;
+
+	if (accessor == SIDE) {
+		this->do_write_line(data_line, address);
+		r = OK;
+	} else {
+		/* Do this first--then process the first cycle immediately. */
+		if (this->requester == IDLE)
+			this->requester = accessor;
+
+		if (this->requester == accessor) {
+			if (this->wait_time == 0) {
+				this->do_write_line(data_line, address);
+				r = OK;
+			}
+		}
+	}
+	return r;
+}
+
+Response Dram::write_word(Accessor accessor, signed int data, int address)
 {
 	Response r = WAIT;
 
@@ -51,14 +94,27 @@ Response Dram::write(Accessor accessor, signed int data, int address)
 	return r;
 }
 
-void Dram::do_read(std::array<signed int, LINE_SIZE> &data_line, int address)
+Response Dram::read_line(
+	Accessor accessor,
+	int address,
+	std::array<signed int, LINE_SIZE> &data_line)
 {
-	int line = address / LINE_SIZE;
-	data_line = this->data->at(line);
+	Response r = WAIT;
+
+	if (this->requester == IDLE)
+		this->requester = accessor;
+
+	if (this->requester == accessor) {
+		if (this->wait_time == 0) {
+			this->do_read(data_line, address);
+			r = OK;
+		}
+	}
+
+	return r;
 }
 
-Response Dram::read(
-	Accessor accessor, int address, std::array<signed int, LINE_SIZE> &data)
+Response Dram::read_word(Accessor accessor, int address, signed int &data)
 {
 	Response r = WAIT;
 
@@ -67,7 +123,7 @@ Response Dram::read(
 
 	if (this->requester == accessor) {
 		if (this->wait_time == 0) {
-			this->do_read(data, address);
+			this->do_read_word(data, address);
 			r = OK;
 		}
 	}
diff --git a/src/utils/utils.cc b/src/utils/utils.cc
index 5de8e89..f95d88f 100644
--- a/src/utils/utils.cc
+++ b/src/utils/utils.cc
@@ -28,3 +28,10 @@ const std::string string_format(const char *const zcFormat, ...)
 	va_end(vaArgs);
 	return std::string(zc.data(), iLen);
 }
+
+int wrap_address(int address) {
+	if (address < 0){
+		return ((address % MEM_SIZE) + MEM_SIZE) % MEM_SIZE;
+	}
+	return address % MEM_SIZE;
+}
diff --git a/tests/cache.cc b/tests/cache.cc
index e8a257f..d7b3444 100644
--- a/tests/cache.cc
+++ b/tests/cache.cc
@@ -25,7 +25,7 @@ TEST_CASE("no delay stores instantly", "[cache]")
 
 	Response r;
 
-	r = c->write(MEM, w, 0b0);
+	r = c->write_word(MEM, w, 0b0);
 	CHECK(r == OK);
 	c->resolve();
 
@@ -54,7 +54,7 @@ TEST_CASE("cache takes \"forever\"", "[cache]")
 	int i;
 	Response r;
 	for (i = 0; i < delay + 2; ++i) {
-		r = c->write(MEM, w, 0b0);
+		r = c->write_word(MEM, w, 0b0);
 		CHECK(r == WAIT); // WAIT
 
 		actual = c->view(0, 1)[0];
@@ -62,7 +62,7 @@ TEST_CASE("cache takes \"forever\"", "[cache]")
 		c->resolve();
 	}
 
-	r = c->write(MEM, w, 0b0);
+	r = c->write_word(MEM, w, 0b0);
 	CHECK(r == OK);
 
 	actual = d->view(0, 1)[0];
@@ -90,7 +90,7 @@ TEST_CASE("dram takes \"forever\"", "[cache]")
 	int i;
 	Response r;
 	for (i = 0; i < delay + 2; ++i) {
-		r = c->write(MEM, w, 0b0);
+		r = c->write_word(MEM, w, 0b0);
 		CHECK(r == BLOCKED); // BLOCKED
 
 		actual = c->view(0, 1)[0];
@@ -98,7 +98,7 @@ TEST_CASE("dram takes \"forever\"", "[cache]")
 		c->resolve();
 	}
 
-	r = c->write(MEM, w, 0b0);
+	r = c->write_word(MEM, w, 0b0);
 	CHECK(r == OK);
 
 	actual = d->view(0, 1)[0];
@@ -126,7 +126,7 @@ TEST_CASE("dram and cache take \"forever\"", "[cache]")
 	int i;
 	Response r;
 	for (i = 0; i < delay + 2; ++i) {
-		r = c->write(MEM, w, 0b0);
+		r = c->write_word(MEM, w, 0b0);
 		CHECK(r == BLOCKED); // BLOCKED
 
 		actual = c->view(0, 1)[0];
@@ -135,7 +135,7 @@ TEST_CASE("dram and cache take \"forever\"", "[cache]")
 	}
 
 	for (i = 0; i < delay; ++i) {
-		r = c->write(MEM, w, 0b0);
+		r = c->write_word(MEM, w, 0b0);
 		CHECK(r == WAIT); // WAIT
 
 		actual = c->view(0, 1)[0];
@@ -143,7 +143,7 @@ TEST_CASE("dram and cache take \"forever\"", "[cache]")
 		c->resolve();
 	}
 
-	r = c->write(MEM, w, 0b0);
+	r = c->write_word(MEM, w, 0b0);
 	CHECK(r == OK);
 	c->resolve();
 
@@ -173,10 +173,10 @@ TEST_CASE(
 	int i;
 	Response r;
 	for (i = 0; i < delay + 2; ++i) {
-		r = c->write(MEM, w, 0b0);
+		r = c->write_word(MEM, w, 0b0);
 		CHECK(r == BLOCKED); // BLOCKED
 
-		r = c->write(FETCH, w, 0b1);
+		r = c->write_word(FETCH, w, 0b1);
 		CHECK(r == WAIT); // WAIT
 
 		actual = c->view(0, 1)[0];
@@ -184,9 +184,9 @@ TEST_CASE(
 		c->resolve();
 	}
 
-	r = c->write(MEM, w, 0b0);
+	r = c->write_word(MEM, w, 0b0);
 	CHECK(r == OK);
-	r = c->write(FETCH, w, 0b1);
+	r = c->write_word(FETCH, w, 0b1);
 	CHECK(r == WAIT);
 
 	c->resolve();
@@ -199,7 +199,7 @@ TEST_CASE(
 	actual = c->view(0, 1)[0];
 	REQUIRE(expected == actual);
 
-	r = c->write(FETCH, w, 0b1);
+	r = c->write_word(FETCH, w, 0b1);
 	// this should have been loaded already!
 	CHECK(r == OK);
 
@@ -228,10 +228,10 @@ TEST_CASE(
 	int i;
 	Response r;
 	for (i = 0; i < delay + 2; ++i) {
-		r = c->write(MEM, w, 0b0);
+		r = c->write_word(MEM, w, 0b0);
 		CHECK(r == BLOCKED); // BLOCKED
 
-		r = c->write(FETCH, w, 0b100);
+		r = c->write_word(FETCH, w, 0b100);
 		CHECK(r == WAIT); // WAIT
 
 		actual = c->view(0, 1)[0];
@@ -239,9 +239,9 @@ TEST_CASE(
 		c->resolve();
 	}
 
-	r = c->write(MEM, w, 0b0);
+	r = c->write_word(MEM, w, 0b0);
 	CHECK(r == OK);
-	r = c->write(FETCH, w, 0b1);
+	r = c->write_word(FETCH, w, 0b1);
 	CHECK(r == WAIT);
 
 	c->resolve();
@@ -255,7 +255,7 @@ TEST_CASE(
 	REQUIRE(expected == actual);
 
 	for (i = 0; i < delay + 2; ++i) {
-		r = c->write(FETCH, w, 0b100);
+		r = c->write_word(FETCH, w, 0b100);
 		CHECK(r == BLOCKED); // BLOCKED
 
 		actual = c->view(0, 1)[0];
@@ -263,7 +263,7 @@ TEST_CASE(
 		c->resolve();
 	}
 
-	r = c->write(FETCH, w, 0b1);
+	r = c->write_word(FETCH, w, 0b1);
 	CHECK(r == OK);
 
 	c->resolve();
diff --git a/tests/dram.cc b/tests/dram.cc
index 27fc24f..72a6d14 100644
--- a/tests/dram.cc
+++ b/tests/dram.cc
@@ -22,7 +22,7 @@ TEST_CASE(
 
 	signed int w = 0x11223344;
 
-	Response r = d->write(MEM, w, 0x00000000);
+	Response r = d->write_word(MEM, w, 0x00000000);
 	CHECK(r == OK);
 
 	expected.at(0) = w;
@@ -46,7 +46,7 @@ TEST_CASE(
 	int i;
 	Response r;
 	for (i = 0; i < delay; ++i) {
-		r = d->write(MEM, w, 0x00000000);
+		r = d->write_word(MEM, w, 0x00000000);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -54,7 +54,7 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(MEM, w, 0x00000000);
+	r = d->write_word(MEM, w, 0x00000000);
 	CHECK(r == OK);
 	d->resolve();
 
@@ -81,7 +81,7 @@ TEST_CASE(
 	int i;
 	Response r;
 	for (i = 0; i < delay; ++i) {
-		r = d->write(MEM, w, 0x00000000);
+		r = d->write_word(MEM, w, 0x00000000);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -89,11 +89,11 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(MEM, w, 0x00000000);
+	r = d->write_word(MEM, w, 0x00000000);
 	REQUIRE(r == OK);
 	// clock cycle did NOT resolve yet!
 	// this fetch should not make progress
-	r = d->write(FETCH, w, 0x00000001);
+	r = d->write_word(FETCH, w, 0x00000001);
 	CHECK(r == WAIT);
 
 	actual = d->view(0, 1)[0];
@@ -105,7 +105,7 @@ TEST_CASE(
 	REQUIRE(expected == actual);
 
 	for (i = 0; i < delay; ++i) {
-		r = d->write(FETCH, w, 0x00000001);
+		r = d->write_word(FETCH, w, 0x00000001);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -113,7 +113,7 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(FETCH, w, 0x00000001);
+	r = d->write_word(FETCH, w, 0x00000001);
 	actual = d->view(0, 1)[0];
 	CHECK(r == OK);
 
@@ -140,10 +140,10 @@ TEST_CASE(
 	int i;
 	Response r;
 	for (i = 0; i < delay; ++i) {
-		r = d->write(MEM, w, 0x00000000);
+		r = d->write_word(MEM, w, 0x00000000);
 		CHECK(r == WAIT);
 
-		r = d->write(FETCH, w, 0x00000001);
+		r = d->write_word(FETCH, w, 0x00000001);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -151,9 +151,9 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(MEM, w, 0x00000000);
+	r = d->write_word(MEM, w, 0x00000000);
 	CHECK(r == OK);
-	r = d->write(FETCH, w, 0x00000001);
+	r = d->write_word(FETCH, w, 0x00000001);
 	CHECK(r == WAIT);
 	d->resolve();
 
@@ -162,10 +162,10 @@ TEST_CASE(
 	REQUIRE(expected == actual);
 
 	for (i = 0; i < delay; ++i) {
-		r = d->write(FETCH, w, 0x00000001);
+		r = d->write_word(FETCH, w, 0x00000001);
 		CHECK(r == WAIT);
 
-		r = d->write(MEM, w, 0x00000003);
+		r = d->write_word(MEM, w, 0x00000003);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -173,10 +173,10 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(FETCH, w, 0x00000001);
+	r = d->write_word(FETCH, w, 0x00000001);
 	actual = d->view(0, 1)[0];
 	CHECK(r == OK);
-	r = d->write(MEM, w, 0x00000003);
+	r = d->write_word(MEM, w, 0x00000003);
 	CHECK(r == WAIT);
 
 	expected.at(1) = w;
@@ -186,7 +186,372 @@ TEST_CASE(
 	delete d;
 }
 
-TEST_CASE("Construct singleton dram, write a line to an address, read it in zero cycles", "[dram]")
+TEST_CASE(
+	"Construct singleton dram, store line in zero cycles", "[dram]")
+{
+	Dram *d = new Dram(1, 0);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223344;
+	expected = {w, w+1, w+2, w+3};
+
+	Response r = d->write_line(MEM, expected, 0x00000000);
+	CHECK(r == OK);
+
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE(
+	"Construct singleton dram, store line in three cycles", "[dram]")
+{
+	int delay = 3;
+	Dram *d = new Dram(1, delay);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223344;
+	std::array<signed int, LINE_SIZE> written_line = {w, w+1, w+2, w+3};
+
+	int i;
+	Response r;
+	for (i = 0; i < delay; ++i) {
+		r = d->write_line(MEM, written_line, 0x00000000);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write_line(MEM, written_line, 0x00000000);
+	CHECK(r == OK);
+	d->resolve();
+
+	expected = written_line;
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE(
+	"Construct singleton dram, store line in three cycles no "
+	"conflict",
+	"[dram]")
+{
+	int delay = 3;
+	Dram *d = new Dram(1, delay);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223344;
+	std::array<signed int, LINE_SIZE> written_line = {w, w+1, w+2, w+3};
+
+	int i;
+	Response r;
+	for (i = 0; i < delay; ++i) {
+		r = d->write_line(MEM, written_line, 0x00000000);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write_line(MEM, written_line, 0x00000000);
+	REQUIRE(r == OK);
+	// clock cycle did NOT resolve yet!
+	// this fetch should not make progress
+	r = d->write_line(FETCH, written_line, 0x00000001);
+	CHECK(r == WAIT);
+
+	actual = d->view(0, 1)[0];
+	CHECK(r == WAIT);
+	d->resolve();
+
+	expected = written_line;
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	written_line = {w+4, w+5, w+6, w+7};
+
+	for (i = 0; i < delay; ++i) {
+		r = d->write_line(FETCH, written_line, 0x00000001);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write_line(FETCH, written_line, 0x00000001);
+	actual = d->view(0, 1)[0];
+	CHECK(r == OK);
+
+	expected = written_line;
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE(
+	"Construct singleton dram, store line in three cycles much "
+	"conflict",
+	"[dram]")
+{
+	int delay = 2;
+	Dram *d = new Dram(1, 2);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223344;
+	std::array<signed int, LINE_SIZE> written_line = {w, w+1, w+2, w+3};
+
+	int i;
+	Response r;
+	for (i = 0; i < delay; ++i) {
+		r = d->write_line(MEM, written_line, 0x00000000);
+		CHECK(r == WAIT);
+
+		r = d->write_line(FETCH, written_line, 0x00000001);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write_line(MEM, written_line, 0x00000000);
+	CHECK(r == OK);
+	r = d->write_line(FETCH, written_line, 0x00000001);
+	CHECK(r == WAIT);
+	d->resolve();
+
+	actual = d->view(0, 1)[0];
+	expected = written_line;
+	REQUIRE(expected == actual);
+
+	written_line = {w+4, w+5, w+6, w+7};
+	for (i = 0; i < delay; ++i) {
+		r = d->write_line(FETCH, written_line, 0x00000001);
+		CHECK(r == WAIT);
+
+		r = d->write_line(MEM, written_line, 0x00000003);
+		CHECK(r == WAIT);
+
+		actual = d->view(0, 1)[0];
+		REQUIRE(expected == actual);
+		d->resolve();
+	}
+
+	r = d->write_line(FETCH, written_line, 0x00000001);
+	actual = d->view(0, 1)[0];
+	CHECK(r == OK);
+	r = d->write_line(MEM, written_line, 0x00000003);
+	CHECK(r == WAIT);
+
+	expected = written_line;
+	actual = d->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE("Construct singleton dram, write a line to an address in 0 cycles, read in 0 cycles", "[dram]")
+{
+	Dram *d = new Dram(1, 0);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223311;
+	expected = {w, w+1, w+2, w+3};
+	int addr = 0x00000000;
+	d->write_line(MEM, expected, addr);
+
+	Response r = d->read_line(MEM, 0x00000000, actual);
+	CHECK(r == OK);
+	REQUIRE(expected == actual);
+
+	r = d->read_line(MEM, 0x00000001, actual);
+	CHECK(r == OK);
+	REQUIRE(expected == actual);
+
+	r = d->read_line(MEM, 0x00000002, actual);
+	CHECK(r == OK);
+	REQUIRE(expected == actual);
+
+	r = d->read_line(MEM, 0x00000003, actual);
+	CHECK(r == OK);
+	REQUIRE(expected == actual);
+
+	delete d;
+}
+
+TEST_CASE("Construct singleton dram, write a line to an address in three cycles, read it in three cycles", "[dram]")
+{
+	int delay = 3;
+	Dram *d = new Dram(1, delay);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223311;
+	expected = {w, w+1, w+2, w+3};
+	int addr = 0x00000000;
+	
+	int i;
+	Response r;
+	
+	for(i=0; i<delay; ++i) {
+		r = d->write_line(MEM, expected, addr);
+		d->resolve();
+	}
+	r = d->write_line(MEM, expected, addr);
+	d->resolve();
+
+	for (i = 0; i < delay; ++i) {
+		r = d->read_line(MEM, 0x00000000, actual);
+		CHECK(r == WAIT);
+		REQUIRE(expected != actual);
+		d->resolve();
+	}
+
+	r = d->read_line(MEM, 0x00000000, actual);
+	CHECK(r == OK);
+	d->resolve();
+	REQUIRE(expected == actual);
+	delete d;
+}
+
+TEST_CASE(
+	"Construct singleton dram, store line in 3 cycles, read line in 3 cycles with no conflict","[dram]")
+{
+	int delay = 3;
+	Dram *d = new Dram(1, delay);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223311;
+	expected = {w, w+1, w+2, w+3};
+	int addr = 0x00000000;
+	
+	int i;
+	Response r;
+	for(int j=0; j<delay; ++j) {
+		r = d->write_line(MEM, expected, addr);
+		d->resolve();
+	}
+	r = d->write_line(MEM, expected, addr++);
+	d->resolve();
+
+	for (i = 0; i < delay; ++i) {
+		r = d->read_line(MEM, 0x00000000, actual);
+		CHECK(r == WAIT);
+		REQUIRE(expected != actual);
+		d->resolve();
+	}
+
+	r = d->read_line(MEM, 0x00000000, actual);
+	REQUIRE(r == OK);
+	r = d->read_line(FETCH, 0x00000003, actual);
+	CHECK(r == WAIT); 
+	d->resolve();
+	REQUIRE(expected == actual);
+
+	actual = {0,0,0,0};
+	for (i = 0; i < delay; ++i) {
+		r = d->read_line(FETCH, 0x00000000, actual);
+		CHECK(r == WAIT);
+		REQUIRE(expected != actual);
+		d->resolve();
+	}
+
+	r = d->read_line(FETCH, 0x00000000, actual);
+	REQUIRE(r == OK);
+	r = d->read_line(MEM, 0x00000002, actual);
+	CHECK(r == WAIT);
+	d->resolve();
+	REQUIRE(expected == actual);
+	
+	delete d;
+
+}
+
+TEST_CASE(
+	"Construct singleton dram, store line in 3 cycles, read line in 3 cycles with much conflict","[dram]")
+{
+	int delay = 3;
+	Dram *d = new Dram(1, delay);
+	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
+	std::array<signed int, LINE_SIZE> actual = d->view(0, 1)[0];
+	CHECK(expected == actual);
+
+	signed int w = 0x11223311;
+	expected = {w, w+1, w+2, w+3};
+	int addr = 0x00000000;
+	
+	int i;
+	Response r;
+	for(int j=0; j<delay; ++j) {
+		r = d->write_line(MEM, expected, addr);
+		d->resolve();
+	}
+	r = d->write_line(MEM, expected, addr++);
+	d->resolve();
+
+
+	for (i = 0; i < delay; ++i) {
+		r = d->read_line(MEM, 0x00000000, actual);
+		CHECK(r == WAIT);
+		REQUIRE(expected != actual);
+		r = d->read_line(FETCH, 0x00000002, actual);
+		CHECK(r == WAIT);
+		REQUIRE(expected != actual);
+		d->resolve();
+	}
+
+	r = d->read_line(MEM, 0x00000000, actual);
+	REQUIRE(r == OK);
+	r = d->read_line(FETCH, 0x00000003, actual);
+	CHECK(r == WAIT); 
+	d->resolve();
+	REQUIRE(expected == actual);
+
+	actual = {0,0,0,0};
+	for (i = 0; i < delay; ++i) {
+		r = d->read_line(FETCH, 0x00000000, actual);
+		CHECK(r == WAIT);
+		REQUIRE(expected != actual);
+		r = d->read_line(MEM, 0x00000002, actual);
+		CHECK(r == WAIT);
+		REQUIRE(expected != actual);
+		d->resolve();
+	}
+
+	r = d->read_line(FETCH, 0x00000000, actual);
+	REQUIRE(r == OK);
+	r = d->read_line(MEM, 0x00000002, actual);
+	CHECK(r == WAIT);
+	d->resolve();
+	REQUIRE(expected == actual);
+	
+	delete d;
+
+}
+
+
+TEST_CASE("Construct singleton dram, write a line to an address one element at a time, read it in zero cycles", "[dram]")
 {
 	Dram *d = new Dram(1, 0);
 	std::array<signed int, LINE_SIZE> expected = {0, 0, 0, 0};
@@ -196,31 +561,31 @@ TEST_CASE("Construct singleton dram, write a line to an address, read it in zero
 	signed int w = 0x11223311;
 	int addr = 0x00000000;
 	for(int i=0; i<LINE_SIZE; ++i) {
-		Response r = d->write(MEM, w, addr++);
+		Response r = d->write_word(MEM, w, addr++);
 		CHECK(r == OK);
 		expected.at(i) = w++;
 	}
 
-	Response r = d->read(MEM, 0x00000000, actual);
+	Response r = d->read_line(MEM, 0x00000000, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
-	r = d->read(MEM, 0x00000001, actual);
+	r = d->read_line(MEM, 0x00000001, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
-	r = d->read(MEM, 0x00000002, actual);
+	r = d->read_line(MEM, 0x00000002, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
-	r = d->read(MEM, 0x00000003, actual);
+	r = d->read_line(MEM, 0x00000003, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
 	delete d;
 }
 
-TEST_CASE("Construct singleton dram, write a line to an address in 12 cycles, read it in three cycles", "[dram]")
+TEST_CASE("Construct singleton dram, write a line to an address one element at a time in 12 cycles, read it in three cycles", "[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -234,22 +599,22 @@ TEST_CASE("Construct singleton dram, write a line to an address in 12 cycles, re
 	Response r;
 	for(i=0; i<LINE_SIZE; ++i) {
 		for(int j=0; j<delay; ++j) {
-			r = d->write(MEM, w, addr);
+			r = d->write_word(MEM, w, addr);
 			d->resolve();
 		}
-		r = d->write(MEM, w, addr++);
+		r = d->write_word(MEM, w, addr++);
 		d->resolve();
 		expected.at(i) = w++;
 	}
 
 	for (i = 0; i < delay; ++i) {
-		r = d->read(MEM, 0x00000000, actual);
+		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(MEM, 0x00000000, actual);
+	r = d->read_line(MEM, 0x00000000, actual);
 	CHECK(r == OK);
 	d->resolve();
 	REQUIRE(expected == actual);
@@ -257,7 +622,7 @@ TEST_CASE("Construct singleton dram, write a line to an address in 12 cycles, re
 }
 
 TEST_CASE(
-	"Construct singleton dram, store line in 12 cycles, read line in 3 cycles with no conflict","[dram]")
+	"Construct singleton dram, store line one element at a time in 12 cycles, read line in 3 cycles with no conflict","[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -271,39 +636,39 @@ TEST_CASE(
 	Response r;
 	for(i=0; i<LINE_SIZE; ++i) {
 		for(int j=0; j<delay; ++j) {
-			r = d->write(MEM, w, addr);
+			r = d->write_word(MEM, w, addr);
 			d->resolve();
 		}
-		r = d->write(MEM, w, addr++);
+		r = d->write_word(MEM, w, addr++);
 		d->resolve();
 		expected.at(i) = w++;
 	}
 
 	for (i = 0; i < delay; ++i) {
-		r = d->read(MEM, 0x00000000, actual);
+		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(MEM, 0x00000000, actual);
+	r = d->read_line(MEM, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(FETCH, 0x00000003, actual);
+	r = d->read_line(FETCH, 0x00000003, actual);
 	CHECK(r == WAIT); 
 	d->resolve();
 	REQUIRE(expected == actual);
 
 	actual = {0,0,0,0};
 	for (i = 0; i < delay; ++i) {
-		r = d->read(FETCH, 0x00000000, actual);
+		r = d->read_line(FETCH, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(FETCH, 0x00000000, actual);
+	r = d->read_line(FETCH, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(MEM, 0x00000002, actual);
+	r = d->read_line(MEM, 0x00000002, actual);
 	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
@@ -313,7 +678,7 @@ TEST_CASE(
 }
 
 TEST_CASE(
-	"Construct singleton dram, store line in 12 cycles, read line in 3 cycles with much conflict","[dram]")
+	"Construct singleton dram, store line one element at a time in 12 cycles, read line in 3 cycles with much conflict","[dram]")
 {
 	int delay = 3;
 	Dram *d = new Dram(1, delay);
@@ -327,45 +692,45 @@ TEST_CASE(
 	Response r;
 	for(i=0; i<LINE_SIZE; ++i) {
 		for(int j=0; j<delay; ++j) {
-			r = d->write(MEM, w, addr);
+			r = d->write_word(MEM, w, addr);
 			d->resolve();
 		}
-		r = d->write(MEM, w, addr++);
+		r = d->write_word(MEM, w, addr++);
 		d->resolve();
 		expected.at(i) = w++;
 	}
 
 	for (i = 0; i < delay; ++i) {
-		r = d->read(MEM, 0x00000000, actual);
+		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
-		r = d->read(FETCH, 0x00000002, actual);
+		r = d->read_line(FETCH, 0x00000002, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(MEM, 0x00000000, actual);
+	r = d->read_line(MEM, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(FETCH, 0x00000003, actual);
+	r = d->read_line(FETCH, 0x00000003, actual);
 	CHECK(r == WAIT); 
 	d->resolve();
 	REQUIRE(expected == actual);
 
 	actual = {0,0,0,0};
 	for (i = 0; i < delay; ++i) {
-		r = d->read(FETCH, 0x00000000, actual);
+		r = d->read_line(FETCH, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
-		r = d->read(MEM, 0x00000002, actual);
+		r = d->read_line(MEM, 0x00000002, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(FETCH, 0x00000000, actual);
+	r = d->read_line(FETCH, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(MEM, 0x00000002, actual);
+	r = d->read_line(MEM, 0x00000002, actual);
 	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
@@ -388,7 +753,7 @@ TEST_CASE("Sidedoor bypasses delay", "[dram]")
 	int i;
 	Response r;
 	for (i = 0; i < delay - 1; ++i) {
-		r = d->write(MEM, w, 0x00000000);
+		r = d->write_word(MEM, w, 0x00000000);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -396,12 +761,12 @@ TEST_CASE("Sidedoor bypasses delay", "[dram]")
 		d->resolve();
 	}
 
-	r = d->write(MEM, w, 0x00000000);
+	r = d->write_word(MEM, w, 0x00000000);
 	CHECK(r == WAIT);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
 
-	r = d->write(SIDE, w, 0x00000001);
+	r = d->write_word(SIDE, w, 0x00000001);
 	actual = d->view(0, 1)[0];
 	CHECK(r == OK);
 
diff --git a/tests/utils.cc b/tests/utils.cc
index 5368204..f0e4c24 100644
--- a/tests/utils.cc
+++ b/tests/utils.cc
@@ -21,3 +21,45 @@ TEST_CASE("Parse arbitrary fields # two", "[cache]")
 	CHECK(index == 0b01110);
 	CHECK(offset == 0b11);
 }
+
+TEST_CASE("wrap address outside upper bound", "[utils]")
+{
+	int address = MEM_SIZE + 25;
+	int wrapped = wrap_address(address);
+	REQUIRE(wrapped == 25);
+}
+
+TEST_CASE("wrap address inside upper bound", "[utils]")
+{
+	int address = MEM_SIZE - 25;
+	int wrapped = wrap_address(address);
+	REQUIRE(wrapped == MEM_SIZE - 25);
+}
+
+TEST_CASE("wrap address at upper bound", "[utils]")
+{
+	int address = MEM_SIZE;
+	int wrapped = wrap_address(address);
+	REQUIRE(wrapped == 0);
+}
+
+TEST_CASE("wrap address lower than 0 with magnitude lesser than mem size", "[utils]")
+{
+	int address = -10;
+	int wrapped = wrap_address(address);
+	REQUIRE(wrapped == MEM_SIZE - 10);
+}
+
+TEST_CASE("wrap address lower than 0 but with magnitude greater than mem size", "[utils]")
+{
+	int address = -(MEM_SIZE + 10);
+	int wrapped = wrap_address(address);
+	REQUIRE(wrapped == MEM_SIZE - 10);
+}
+
+TEST_CASE("wrap address at 0", "[utils]")
+{
+	int address = 0;
+	int wrapped = wrap_address(address);
+	REQUIRE(wrapped == 0);
+}
\ No newline at end of file