Rename read/write to read_line and write_word

8 files changed, 125 insertions, 110 deletions

diff --git a/inc/cache.h b/inc/cache.h
index 20a40c2..17abcdd 100644
--- a/inc/cache.h
+++ b/inc/cache.h
@@ -20,13 +20,18 @@ class Cache : public Storage
 	Cache(Storage *lower, int delay);
 	~Cache();
 
-	Response write(Accessor accessor, signed int data, int address) override;
-	Response write_line(Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address) override;
-	Response read(
+	Response
+	write_word(Accessor accessor, signed int data, int address) override;
+	Response write_line(
+		Accessor accessor,
+		std::array<signed int, LINE_SIZE> data_line,
+		int address) override;
+	Response read_line(
 		Accessor accessor,
 		int address,
 		std::array<signed int, LINE_SIZE> &data_line) override;
-	Response read_word(Accessor accessor, int address, signed int &data) override;
+	Response
+	read_word(Accessor accessor, int address, signed int &data) override;
 
 	/**
 	 * Getter for the meta attribute.
diff --git a/inc/dram.h b/inc/dram.h
index 7774040..2771c3e 100644
--- a/inc/dram.h
+++ b/inc/dram.h
@@ -17,15 +17,20 @@ class Dram : public Storage
 	Dram(int lines, int delay);
 	~Dram();
 
-	Response write(Accessor accessor, signed int data, int address) override;
-	Response read(
+	Response
+	write_word(Accessor accessor, signed int data, int address) override;
+	Response read_line(
 		Accessor accessor,
 		int address,
 		std::array<signed int, LINE_SIZE> &data_line) override;
-	Response write_line(Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address) override;
-	Response read_word(Accessor accessor, int address, signed int &data) override;
+	Response write_line(
+		Accessor accessor,
+		std::array<signed int, LINE_SIZE> data_line,
+		int address) override;
+	Response
+	read_word(Accessor accessor, int address, signed int &data) override;
 
-	private:
+  private:
 	/**
 	 * Helper for `write` a word
 	 */
@@ -33,7 +38,8 @@ class Dram : public Storage
 	/**
 	 * Helper for writing a line.
 	 */
-	void do_write_line(std::array<signed int, LINE_SIZE> data_line, int address);
+	void
+	do_write_line(std::array<signed int, LINE_SIZE> data_line, int address);
 	/**
 	 * Helper for `read` a line
 	 */
diff --git a/inc/storage.h b/inc/storage.h
index fc93d7a..b54a6f7 100644
--- a/inc/storage.h
+++ b/inc/storage.h
@@ -20,7 +20,7 @@ class Storage
 	 * @param the address to write to.
 	 * @return a status code reflecting the state of the request.
 	 */
-	virtual Response write(Accessor accessor, signed int data, int address) = 0;
+	virtual Response write_word(Accessor accessor, signed int data, int address) = 0;
 
 	/**
 	 * Write a data line to given address in this level of storage
@@ -35,7 +35,7 @@ class Storage
 	 * @return a status code reflecting the state of the request, and the
 	 * data being returned.
 	 */
-	virtual Response read(
+	virtual Response read_line(
 		Accessor accessor,
 		int address,
 		std::array<signed int, LINE_SIZE> &data) = 0;
diff --git a/src/cli/cli.cc b/src/cli/cli.cc
index 0729e00..a885aee 100644
--- a/src/cli/cli.cc
+++ b/src/cli/cli.cc
@@ -115,7 +115,7 @@ void Cli::load(Accessor accessor, int address)
 
 void Cli::store(Accessor accessor, int data, int address)
 {
-	Response r = this->cache->write(accessor, data, address);
+	Response r = this->cache->write_word(accessor, data, address);
 	std::cout << r << " to " << accessor << " storing " << data << " in"
 			  << address << std::endl;
 }
diff --git a/src/storage/cache.cc b/src/storage/cache.cc
index 5e071ac..533d0ec 100644
--- a/src/storage/cache.cc
+++ b/src/storage/cache.cc
@@ -25,7 +25,7 @@ Cache::~Cache()
 	delete this->data;
 }
 
-Response Cache::write(Accessor accessor, signed int data, int address)
+Response Cache::write_word(Accessor accessor, signed int data, int address)
 {
 	Response r = WAIT;
 
@@ -75,7 +75,7 @@ Response Cache::write_line(
 }
 
 // TODO: tests for multi level cache
-Response Cache::read(
+Response Cache::read_line(
 	Accessor accessor,
 	int address,
 	std::array<signed int, LINE_SIZE> &data_line)
@@ -140,7 +140,7 @@ void Cache::fetch_resource(int expected)
 				meta->at(1) = -1;
 			}
 		} else {
-			r = this->lower->read(L1CACHE, expected, actual);
+			r = this->lower->read_line(L1CACHE, expected, actual);
 			if (r == OK) {
 				meta->at(0) = tag;
 			}
diff --git a/src/storage/dram.cc b/src/storage/dram.cc
index 76c4f90..f375a76 100644
--- a/src/storage/dram.cc
+++ b/src/storage/dram.cc
@@ -28,7 +28,9 @@ void Dram::do_write(signed int data, int address)
 	this->data->at(line).at(word) = data;
 }
 
-void Dram::do_write_line(std::array<signed int, LINE_SIZE> data_line, int address){
+void Dram::do_write_line(
+	std::array<signed int, LINE_SIZE> data_line, int address)
+{
 	int line = address / LINE_SIZE;
 	this->data->at(line) = data_line;
 }
@@ -46,9 +48,8 @@ void Dram::do_read_word(signed int &data, int address)
 	data = this->data->at(line).at(word);
 }
 
-
-
-Response Dram::write_line(Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address)
+Response Dram::write_line(
+	Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address)
 {
 	Response r = WAIT;
 
@@ -70,8 +71,7 @@ Response Dram::write_line(Accessor accessor, std::array<signed int, LINE_SIZE> d
 	return r;
 }
 
-
-Response Dram::write(Accessor accessor, signed int data, int address)
+Response Dram::write_word(Accessor accessor, signed int data, int address)
 {
 	Response r = WAIT;
 
@@ -94,7 +94,11 @@ Response Dram::write(Accessor accessor, signed int data, int address)
 	return r;
 }
 
-Response Dram::read(Accessor accessor, int address, std::array<signed int, LINE_SIZE>& data_line) { 
+Response Dram::read_line(
+	Accessor accessor,
+	int address,
+	std::array<signed int, LINE_SIZE> &data_line)
+{
 	Response r = WAIT;
 
 	if (this->requester == IDLE)
@@ -110,7 +114,8 @@ Response Dram::read(Accessor accessor, int address, std::array<signed int, LINE_
 	return r;
 }
 
-Response Dram::read_word(Accessor accessor, int address, signed int& data) { 
+Response Dram::read_word(Accessor accessor, int address, signed int &data)
+{
 	Response r = WAIT;
 
 	if (this->requester == IDLE)
@@ -149,4 +154,3 @@ std::ostream &operator<<(std::ostream &os, const Dram &d)
 	std::cout.fill(default_fill);
 	return os;
 }
-
diff --git a/tests/cache.cc b/tests/cache.cc
index e8a257f..d7b3444 100644
--- a/tests/cache.cc
+++ b/tests/cache.cc
@@ -25,7 +25,7 @@ TEST_CASE("no delay stores instantly", "[cache]")
 
 	Response r;
 
-	r = c->write(MEM, w, 0b0);
+	r = c->write_word(MEM, w, 0b0);
 	CHECK(r == OK);
 	c->resolve();
 
@@ -54,7 +54,7 @@ TEST_CASE("cache takes \"forever\"", "[cache]")
 	int i;
 	Response r;
 	for (i = 0; i < delay + 2; ++i) {
-		r = c->write(MEM, w, 0b0);
+		r = c->write_word(MEM, w, 0b0);
 		CHECK(r == WAIT); // WAIT
 
 		actual = c->view(0, 1)[0];
@@ -62,7 +62,7 @@ TEST_CASE("cache takes \"forever\"", "[cache]")
 		c->resolve();
 	}
 
-	r = c->write(MEM, w, 0b0);
+	r = c->write_word(MEM, w, 0b0);
 	CHECK(r == OK);
 
 	actual = d->view(0, 1)[0];
@@ -90,7 +90,7 @@ TEST_CASE("dram takes \"forever\"", "[cache]")
 	int i;
 	Response r;
 	for (i = 0; i < delay + 2; ++i) {
-		r = c->write(MEM, w, 0b0);
+		r = c->write_word(MEM, w, 0b0);
 		CHECK(r == BLOCKED); // BLOCKED
 
 		actual = c->view(0, 1)[0];
@@ -98,7 +98,7 @@ TEST_CASE("dram takes \"forever\"", "[cache]")
 		c->resolve();
 	}
 
-	r = c->write(MEM, w, 0b0);
+	r = c->write_word(MEM, w, 0b0);
 	CHECK(r == OK);
 
 	actual = d->view(0, 1)[0];
@@ -126,7 +126,7 @@ TEST_CASE("dram and cache take \"forever\"", "[cache]")
 	int i;
 	Response r;
 	for (i = 0; i < delay + 2; ++i) {
-		r = c->write(MEM, w, 0b0);
+		r = c->write_word(MEM, w, 0b0);
 		CHECK(r == BLOCKED); // BLOCKED
 
 		actual = c->view(0, 1)[0];
@@ -135,7 +135,7 @@ TEST_CASE("dram and cache take \"forever\"", "[cache]")
 	}
 
 	for (i = 0; i < delay; ++i) {
-		r = c->write(MEM, w, 0b0);
+		r = c->write_word(MEM, w, 0b0);
 		CHECK(r == WAIT); // WAIT
 
 		actual = c->view(0, 1)[0];
@@ -143,7 +143,7 @@ TEST_CASE("dram and cache take \"forever\"", "[cache]")
 		c->resolve();
 	}
 
-	r = c->write(MEM, w, 0b0);
+	r = c->write_word(MEM, w, 0b0);
 	CHECK(r == OK);
 	c->resolve();
 
@@ -173,10 +173,10 @@ TEST_CASE(
 	int i;
 	Response r;
 	for (i = 0; i < delay + 2; ++i) {
-		r = c->write(MEM, w, 0b0);
+		r = c->write_word(MEM, w, 0b0);
 		CHECK(r == BLOCKED); // BLOCKED
 
-		r = c->write(FETCH, w, 0b1);
+		r = c->write_word(FETCH, w, 0b1);
 		CHECK(r == WAIT); // WAIT
 
 		actual = c->view(0, 1)[0];
@@ -184,9 +184,9 @@ TEST_CASE(
 		c->resolve();
 	}
 
-	r = c->write(MEM, w, 0b0);
+	r = c->write_word(MEM, w, 0b0);
 	CHECK(r == OK);
-	r = c->write(FETCH, w, 0b1);
+	r = c->write_word(FETCH, w, 0b1);
 	CHECK(r == WAIT);
 
 	c->resolve();
@@ -199,7 +199,7 @@ TEST_CASE(
 	actual = c->view(0, 1)[0];
 	REQUIRE(expected == actual);
 
-	r = c->write(FETCH, w, 0b1);
+	r = c->write_word(FETCH, w, 0b1);
 	// this should have been loaded already!
 	CHECK(r == OK);
 
@@ -228,10 +228,10 @@ TEST_CASE(
 	int i;
 	Response r;
 	for (i = 0; i < delay + 2; ++i) {
-		r = c->write(MEM, w, 0b0);
+		r = c->write_word(MEM, w, 0b0);
 		CHECK(r == BLOCKED); // BLOCKED
 
-		r = c->write(FETCH, w, 0b100);
+		r = c->write_word(FETCH, w, 0b100);
 		CHECK(r == WAIT); // WAIT
 
 		actual = c->view(0, 1)[0];
@@ -239,9 +239,9 @@ TEST_CASE(
 		c->resolve();
 	}
 
-	r = c->write(MEM, w, 0b0);
+	r = c->write_word(MEM, w, 0b0);
 	CHECK(r == OK);
-	r = c->write(FETCH, w, 0b1);
+	r = c->write_word(FETCH, w, 0b1);
 	CHECK(r == WAIT);
 
 	c->resolve();
@@ -255,7 +255,7 @@ TEST_CASE(
 	REQUIRE(expected == actual);
 
 	for (i = 0; i < delay + 2; ++i) {
-		r = c->write(FETCH, w, 0b100);
+		r = c->write_word(FETCH, w, 0b100);
 		CHECK(r == BLOCKED); // BLOCKED
 
 		actual = c->view(0, 1)[0];
@@ -263,7 +263,7 @@ TEST_CASE(
 		c->resolve();
 	}
 
-	r = c->write(FETCH, w, 0b1);
+	r = c->write_word(FETCH, w, 0b1);
 	CHECK(r == OK);
 
 	c->resolve();
diff --git a/tests/dram.cc b/tests/dram.cc
index 8425d3b..72a6d14 100644
--- a/tests/dram.cc
+++ b/tests/dram.cc
@@ -22,7 +22,7 @@ TEST_CASE(
 
 	signed int w = 0x11223344;
 
-	Response r = d->write(MEM, w, 0x00000000);
+	Response r = d->write_word(MEM, w, 0x00000000);
 	CHECK(r == OK);
 
 	expected.at(0) = w;
@@ -46,7 +46,7 @@ TEST_CASE(
 	int i;
 	Response r;
 	for (i = 0; i < delay; ++i) {
-		r = d->write(MEM, w, 0x00000000);
+		r = d->write_word(MEM, w, 0x00000000);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -54,7 +54,7 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(MEM, w, 0x00000000);
+	r = d->write_word(MEM, w, 0x00000000);
 	CHECK(r == OK);
 	d->resolve();
 
@@ -81,7 +81,7 @@ TEST_CASE(
 	int i;
 	Response r;
 	for (i = 0; i < delay; ++i) {
-		r = d->write(MEM, w, 0x00000000);
+		r = d->write_word(MEM, w, 0x00000000);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -89,11 +89,11 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(MEM, w, 0x00000000);
+	r = d->write_word(MEM, w, 0x00000000);
 	REQUIRE(r == OK);
 	// clock cycle did NOT resolve yet!
 	// this fetch should not make progress
-	r = d->write(FETCH, w, 0x00000001);
+	r = d->write_word(FETCH, w, 0x00000001);
 	CHECK(r == WAIT);
 
 	actual = d->view(0, 1)[0];
@@ -105,7 +105,7 @@ TEST_CASE(
 	REQUIRE(expected == actual);
 
 	for (i = 0; i < delay; ++i) {
-		r = d->write(FETCH, w, 0x00000001);
+		r = d->write_word(FETCH, w, 0x00000001);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -113,7 +113,7 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(FETCH, w, 0x00000001);
+	r = d->write_word(FETCH, w, 0x00000001);
 	actual = d->view(0, 1)[0];
 	CHECK(r == OK);
 
@@ -140,10 +140,10 @@ TEST_CASE(
 	int i;
 	Response r;
 	for (i = 0; i < delay; ++i) {
-		r = d->write(MEM, w, 0x00000000);
+		r = d->write_word(MEM, w, 0x00000000);
 		CHECK(r == WAIT);
 
-		r = d->write(FETCH, w, 0x00000001);
+		r = d->write_word(FETCH, w, 0x00000001);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -151,9 +151,9 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(MEM, w, 0x00000000);
+	r = d->write_word(MEM, w, 0x00000000);
 	CHECK(r == OK);
-	r = d->write(FETCH, w, 0x00000001);
+	r = d->write_word(FETCH, w, 0x00000001);
 	CHECK(r == WAIT);
 	d->resolve();
 
@@ -162,10 +162,10 @@ TEST_CASE(
 	REQUIRE(expected == actual);
 
 	for (i = 0; i < delay; ++i) {
-		r = d->write(FETCH, w, 0x00000001);
+		r = d->write_word(FETCH, w, 0x00000001);
 		CHECK(r == WAIT);
 
-		r = d->write(MEM, w, 0x00000003);
+		r = d->write_word(MEM, w, 0x00000003);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -173,10 +173,10 @@ TEST_CASE(
 		d->resolve();
 	}
 
-	r = d->write(FETCH, w, 0x00000001);
+	r = d->write_word(FETCH, w, 0x00000001);
 	actual = d->view(0, 1)[0];
 	CHECK(r == OK);
-	r = d->write(MEM, w, 0x00000003);
+	r = d->write_word(MEM, w, 0x00000003);
 	CHECK(r == WAIT);
 
 	expected.at(1) = w;
@@ -378,19 +378,19 @@ TEST_CASE("Construct singleton dram, write a line to an address in 0 cycles, rea
 	int addr = 0x00000000;
 	d->write_line(MEM, expected, addr);
 
-	Response r = d->read(MEM, 0x00000000, actual);
+	Response r = d->read_line(MEM, 0x00000000, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
-	r = d->read(MEM, 0x00000001, actual);
+	r = d->read_line(MEM, 0x00000001, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
-	r = d->read(MEM, 0x00000002, actual);
+	r = d->read_line(MEM, 0x00000002, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
-	r = d->read(MEM, 0x00000003, actual);
+	r = d->read_line(MEM, 0x00000003, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
@@ -420,13 +420,13 @@ TEST_CASE("Construct singleton dram, write a line to an address in three cycles,
 	d->resolve();
 
 	for (i = 0; i < delay; ++i) {
-		r = d->read(MEM, 0x00000000, actual);
+		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(MEM, 0x00000000, actual);
+	r = d->read_line(MEM, 0x00000000, actual);
 	CHECK(r == OK);
 	d->resolve();
 	REQUIRE(expected == actual);
@@ -456,30 +456,30 @@ TEST_CASE(
 	d->resolve();
 
 	for (i = 0; i < delay; ++i) {
-		r = d->read(MEM, 0x00000000, actual);
+		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(MEM, 0x00000000, actual);
+	r = d->read_line(MEM, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(FETCH, 0x00000003, actual);
+	r = d->read_line(FETCH, 0x00000003, actual);
 	CHECK(r == WAIT); 
 	d->resolve();
 	REQUIRE(expected == actual);
 
 	actual = {0,0,0,0};
 	for (i = 0; i < delay; ++i) {
-		r = d->read(FETCH, 0x00000000, actual);
+		r = d->read_line(FETCH, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(FETCH, 0x00000000, actual);
+	r = d->read_line(FETCH, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(MEM, 0x00000002, actual);
+	r = d->read_line(MEM, 0x00000002, actual);
 	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
@@ -512,36 +512,36 @@ TEST_CASE(
 
 
 	for (i = 0; i < delay; ++i) {
-		r = d->read(MEM, 0x00000000, actual);
+		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
-		r = d->read(FETCH, 0x00000002, actual);
+		r = d->read_line(FETCH, 0x00000002, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(MEM, 0x00000000, actual);
+	r = d->read_line(MEM, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(FETCH, 0x00000003, actual);
+	r = d->read_line(FETCH, 0x00000003, actual);
 	CHECK(r == WAIT); 
 	d->resolve();
 	REQUIRE(expected == actual);
 
 	actual = {0,0,0,0};
 	for (i = 0; i < delay; ++i) {
-		r = d->read(FETCH, 0x00000000, actual);
+		r = d->read_line(FETCH, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
-		r = d->read(MEM, 0x00000002, actual);
+		r = d->read_line(MEM, 0x00000002, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(FETCH, 0x00000000, actual);
+	r = d->read_line(FETCH, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(MEM, 0x00000002, actual);
+	r = d->read_line(MEM, 0x00000002, actual);
 	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
@@ -561,24 +561,24 @@ TEST_CASE("Construct singleton dram, write a line to an address one element at a
 	signed int w = 0x11223311;
 	int addr = 0x00000000;
 	for(int i=0; i<LINE_SIZE; ++i) {
-		Response r = d->write(MEM, w, addr++);
+		Response r = d->write_word(MEM, w, addr++);
 		CHECK(r == OK);
 		expected.at(i) = w++;
 	}
 
-	Response r = d->read(MEM, 0x00000000, actual);
+	Response r = d->read_line(MEM, 0x00000000, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
-	r = d->read(MEM, 0x00000001, actual);
+	r = d->read_line(MEM, 0x00000001, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
-	r = d->read(MEM, 0x00000002, actual);
+	r = d->read_line(MEM, 0x00000002, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
-	r = d->read(MEM, 0x00000003, actual);
+	r = d->read_line(MEM, 0x00000003, actual);
 	CHECK(r == OK);
 	REQUIRE(expected == actual);
 
@@ -599,22 +599,22 @@ TEST_CASE("Construct singleton dram, write a line to an address one element at a
 	Response r;
 	for(i=0; i<LINE_SIZE; ++i) {
 		for(int j=0; j<delay; ++j) {
-			r = d->write(MEM, w, addr);
+			r = d->write_word(MEM, w, addr);
 			d->resolve();
 		}
-		r = d->write(MEM, w, addr++);
+		r = d->write_word(MEM, w, addr++);
 		d->resolve();
 		expected.at(i) = w++;
 	}
 
 	for (i = 0; i < delay; ++i) {
-		r = d->read(MEM, 0x00000000, actual);
+		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(MEM, 0x00000000, actual);
+	r = d->read_line(MEM, 0x00000000, actual);
 	CHECK(r == OK);
 	d->resolve();
 	REQUIRE(expected == actual);
@@ -636,39 +636,39 @@ TEST_CASE(
 	Response r;
 	for(i=0; i<LINE_SIZE; ++i) {
 		for(int j=0; j<delay; ++j) {
-			r = d->write(MEM, w, addr);
+			r = d->write_word(MEM, w, addr);
 			d->resolve();
 		}
-		r = d->write(MEM, w, addr++);
+		r = d->write_word(MEM, w, addr++);
 		d->resolve();
 		expected.at(i) = w++;
 	}
 
 	for (i = 0; i < delay; ++i) {
-		r = d->read(MEM, 0x00000000, actual);
+		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(MEM, 0x00000000, actual);
+	r = d->read_line(MEM, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(FETCH, 0x00000003, actual);
+	r = d->read_line(FETCH, 0x00000003, actual);
 	CHECK(r == WAIT); 
 	d->resolve();
 	REQUIRE(expected == actual);
 
 	actual = {0,0,0,0};
 	for (i = 0; i < delay; ++i) {
-		r = d->read(FETCH, 0x00000000, actual);
+		r = d->read_line(FETCH, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(FETCH, 0x00000000, actual);
+	r = d->read_line(FETCH, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(MEM, 0x00000002, actual);
+	r = d->read_line(MEM, 0x00000002, actual);
 	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
@@ -692,45 +692,45 @@ TEST_CASE(
 	Response r;
 	for(i=0; i<LINE_SIZE; ++i) {
 		for(int j=0; j<delay; ++j) {
-			r = d->write(MEM, w, addr);
+			r = d->write_word(MEM, w, addr);
 			d->resolve();
 		}
-		r = d->write(MEM, w, addr++);
+		r = d->write_word(MEM, w, addr++);
 		d->resolve();
 		expected.at(i) = w++;
 	}
 
 	for (i = 0; i < delay; ++i) {
-		r = d->read(MEM, 0x00000000, actual);
+		r = d->read_line(MEM, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
-		r = d->read(FETCH, 0x00000002, actual);
+		r = d->read_line(FETCH, 0x00000002, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(MEM, 0x00000000, actual);
+	r = d->read_line(MEM, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(FETCH, 0x00000003, actual);
+	r = d->read_line(FETCH, 0x00000003, actual);
 	CHECK(r == WAIT); 
 	d->resolve();
 	REQUIRE(expected == actual);
 
 	actual = {0,0,0,0};
 	for (i = 0; i < delay; ++i) {
-		r = d->read(FETCH, 0x00000000, actual);
+		r = d->read_line(FETCH, 0x00000000, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
-		r = d->read(MEM, 0x00000002, actual);
+		r = d->read_line(MEM, 0x00000002, actual);
 		CHECK(r == WAIT);
 		REQUIRE(expected != actual);
 		d->resolve();
 	}
 
-	r = d->read(FETCH, 0x00000000, actual);
+	r = d->read_line(FETCH, 0x00000000, actual);
 	REQUIRE(r == OK);
-	r = d->read(MEM, 0x00000002, actual);
+	r = d->read_line(MEM, 0x00000002, actual);
 	CHECK(r == WAIT);
 	d->resolve();
 	REQUIRE(expected == actual);
@@ -753,7 +753,7 @@ TEST_CASE("Sidedoor bypasses delay", "[dram]")
 	int i;
 	Response r;
 	for (i = 0; i < delay - 1; ++i) {
-		r = d->write(MEM, w, 0x00000000);
+		r = d->write_word(MEM, w, 0x00000000);
 		CHECK(r == WAIT);
 
 		actual = d->view(0, 1)[0];
@@ -761,12 +761,12 @@ TEST_CASE("Sidedoor bypasses delay", "[dram]")
 		d->resolve();
 	}
 
-	r = d->write(MEM, w, 0x00000000);
+	r = d->write_word(MEM, w, 0x00000000);
 	CHECK(r == WAIT);
 	actual = d->view(0, 1)[0];
 	REQUIRE(expected == actual);
 
-	r = d->write(SIDE, w, 0x00000001);
+	r = d->write_word(SIDE, w, 0x00000001);
 	actual = d->view(0, 1)[0];
 	CHECK(r == OK);