support for reading word, writing line to storage, dirty cache eviction, cache load

6 files changed, 110 insertions, 13 deletions

diff --git a/inc/cache.h b/inc/cache.h
index 5cdcea4..bc37f54 100644
--- a/inc/cache.h
+++ b/inc/cache.h
@@ -21,11 +21,12 @@ class Cache : public Storage
 	~Cache();
 
 	Response write(Accessor accessor, signed int data, int address) override;
+	Response write_line(Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address) override;
 	Response read(
 		Accessor accessor,
 		int address,
 		std::array<signed int, LINE_SIZE> &data) override;
-	Response read_word(Accessor accessor, int address, signed int &data);
+	Response read_word(Accessor accessor, int address, signed int &data) override;
 
 	/**
 	 * Getter for the meta attribute.
diff --git a/inc/dram.h b/inc/dram.h
index d68797f..427500c 100644
--- a/inc/dram.h
+++ b/inc/dram.h
@@ -22,18 +22,29 @@ class Dram : public Storage
 		Accessor accessor,
 		int address,
 		std::array<signed int, LINE_SIZE> &data) override;
+	Response write_line(Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address) override;
 
-	void write_line(std::array<signed int, LINE_SIZE> data_line, int address);
+	Response read(Accessor accessor, int address, std::array<signed int, LINE_SIZE>& data) override;
+	Response read_word(Accessor accessor, int address, signed int &data) override;
 
 	private:
 	/**
-	 * Helper for `write`.
+	 * Helper for `write` a word
 	 */
 	void do_write(signed int, int);
 	/**
-	 * Helper for `read`.
+	 * Helper for writing a line.
+	 */
+	void do_write_line(std::array<signed int, LINE_SIZE> data_line, int address);
+	/**
+	 * Helper for `read` a line
 	 */
 	void do_read(std::array<signed int, LINE_SIZE> &data_line, int address);
+	void do_read(std::array<signed int, LINE_SIZE>& data_line, int address);
+	/**
+	 * Helper for reading a word.
+	 */
+	void do_read_word(signed int &data, int address);
 };
 
 std::ostream &operator<<(std::ostream &os, const Dram &d);
diff --git a/inc/storage.h b/inc/storage.h
index a30e74d..fc93d7a 100644
--- a/inc/storage.h
+++ b/inc/storage.h
@@ -14,15 +14,22 @@ class Storage
 	virtual ~Storage() = default;
 
 	/**
-	 * Write `data` into `address`.
+	 * Write `data` word into `address`.
 	 * @param the source making the request.
 	 * @param the data (hexadecimal) to write.
 	 * @param the address to write to.
 	 * @return a status code reflecting the state of the request.
 	 */
 	virtual Response write(Accessor accessor, signed int data, int address) = 0;
+
+	/**
+	 * Write a data line to given address in this level of storage
+	 */
+	virtual Response write_line(Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address) = 0;
+
+	
 	/**
-	 * Get the data at `address`.
+	 * Get the data line at `address`.
 	 * @param the source making the request.
 	 * @param the address being accessed.
 	 * @return a status code reflecting the state of the request, and the
@@ -32,6 +39,12 @@ class Storage
 		Accessor accessor,
 		int address,
 		std::array<signed int, LINE_SIZE> &data) = 0;
+
+	/**
+	 * Read a word from given address in this level of storage
+	 */
+	virtual Response read_word(Accessor accessor, int address, signed int &data) = 0;
+	
 	/**
 	 * Sidedoor view of `lines` of memory starting at `base`.
 	 * @param The base line to start getting memory from.
diff --git a/src/storage/cache.cc b/src/storage/cache.cc
index 66603e2..08699ed 100644
--- a/src/storage/cache.cc
+++ b/src/storage/cache.cc
@@ -49,8 +49,32 @@ Response Cache::write(Accessor accessor, signed int data, int address)
 	return r;
 }
 
+Response Cache::write_line(Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address)
+{
+	Response r = WAIT;
+
+	/* Do this first--then process the first cycle immediately. */
+	if (this->requester == IDLE)
+		this->requester = accessor;
+
+	if (this->requester == accessor) {
+		fetch_resource(address);
+		if (this->is_waiting)
+			r = BLOCKED;
+		else if (this->wait_time == 0) {
+			int tag, index, offset;
+			get_bit_fields(address, &tag, &index, &offset);
+			this->data->at(index) = data_line;
+			this->meta[index].at(1) = 1;
+			r = OK;
+		}
+	}
+
+	return r;
+}
+
 // TODO: tests for multi level cache
-Response Cache::read(Accessor accessor, int address, std::array<signed int, LINE_SIZE> &data)
+Response Cache::read(Accessor accessor, int address, std::array<signed int, LINE_SIZE> &data_line)
 {
 	Response r = WAIT;
 	if (this->requester == IDLE)
@@ -62,7 +86,7 @@ Response Cache::read(Accessor accessor, int address, std::array<signed int, LINE
 		else if (this->wait_time == 0) {
 			int tag, index, offset;
 			get_bit_fields(address, &tag, &index, &offset);
-			data = this->data->at(index);
+			data_line = this->data->at(index);
 			r = OK;
 		}
 	}
@@ -81,7 +105,7 @@ Response Cache::read_word(Accessor accessor, int address, signed int &data)
 		else if (this->wait_time == 0) {
 			int tag, index, offset;
 			get_bit_fields(address, &tag, &index, &offset);
-			data = this->data->at(index)->at(offset);
+			data = this->data->at(index).at(offset);
 			r = OK;
 		}
 	}
diff --git a/src/storage/dram.cc b/src/storage/dram.cc
index 290d38b..be360a4 100644
--- a/src/storage/dram.cc
+++ b/src/storage/dram.cc
@@ -20,7 +20,7 @@ Dram::Dram(int lines, int delay)
 
 Dram::~Dram() { delete this->data; }
 
-void Dram::do_write(signed data, int address)
+void Dram::do_write(signed int data, int address)
 {
 	int line = address / LINE_SIZE;
 	int word = address % LINE_SIZE;
@@ -28,15 +28,46 @@ void Dram::do_write(signed data, int address)
 	this->data->at(line).at(word) = data;
 }
 
+void Dram::do_write_line(std::array<signed int, LINE_SIZE> data_line, int address){
+	int line = address / LINE_SIZE;
+	this->data->at(line) = data_line;
+}
+
 void Dram::do_read(std::array<signed int, LINE_SIZE> &data_line, int address)
 {
 	int line = address / LINE_SIZE;
 	data_line = this->data->at(line);
 }
 
-void Dram::write_line(std::array<signed int, LINE_SIZE> data_line, int address){
+void Dram::do_read_word(signed int &data, int address)
+{
 	int line = address / LINE_SIZE;
-	this->data->at(line) = data_line;
+	int word = address % LINE_SIZE;
+	data = this->data->at(line).at(word);
+}
+
+
+
+Response Dram::write_line(Accessor accessor, std::array<signed int, LINE_SIZE> data_line, int address)
+{
+	Response r = WAIT;
+
+	if (accessor == SIDE) {
+		this->do_write_line(data_line, address);
+		r = OK;
+	} else {
+		/* Do this first--then process the first cycle immediately. */
+		if (this->requester == IDLE)
+			this->requester = accessor;
+
+		if (this->requester == accessor) {
+			if (this->wait_time == 0) {
+				this->do_write_line(data_line, address);
+				r = OK;
+			}
+		}
+	}
+	return r;
 }
 
 
@@ -79,6 +110,22 @@ Response Dram::read(Accessor accessor, int address, std::array<signed int, LINE_
 	return r;
 }
 
+Response Dram::read_word(Accessor accessor, int address, signed int& data) { 
+	Response r = WAIT;
+
+	if (this->requester == IDLE)
+		this->requester = accessor;
+
+	if (this->requester == accessor) {
+		if (this->wait_time == 0) {
+			this->do_read_word(data, address);
+			r = OK;
+		}
+	}
+
+	return r;
+}
+
 std::ostream &operator<<(std::ostream &os, const Dram &d)
 {
 	const auto default_flags = std::cout.flags();
@@ -102,3 +149,4 @@ std::ostream &operator<<(std::ostream &os, const Dram &d)
 	std::cout.fill(default_fill);
 	return os;
 }
+
diff --git a/tests/dram.cc b/tests/dram.cc
index ff0d860..7b19ac4 100644
--- a/tests/dram.cc
+++ b/tests/dram.cc
@@ -196,7 +196,7 @@ TEST_CASE("Construct singleton dram, write a line to an address", "[dram]")
 	signed int w = 0x11223311;
 	expected = {w, w+1, w+2, w+3};
 	int addr = 0x00000000;
-	d->write_line(expected, addr);
+	d->write_line(MEM, expected, addr);
 
 	Response r = d->read(MEM, 0x00000000, actual);
 	CHECK(r == OK);