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authorbd <bdunahu@operationnull.com>2025-04-11 20:52:19 -0400
committerbd <bdunahu@operationnull.com>2025-04-11 20:52:19 -0400
commit7a63a61ac7d4a3e4a6667055ea55db1c55779a23 (patch)
tree7bd6ca943e97737d68a03fab900b0f7f18079e1e /README.md
parent4181123e760abb9e6f4e753925f4aa24cf0eea85 (diff)
Modify README and CMakeLists from repository split
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diff --git a/README.md b/README.md
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-# Risc V[ECTOR]
+# ram
-## Corresponding Assembler can be found here
-`https://github.com/bdunahu/rva`
+##
-## dependencies
-- cmake
-- g++ (GCC) 11.4.0
-- catch2 version 3.5.3
-- Qt version 6.8.2
+This is a cache and memory simulator for a custom ISA nicknamed "RISC V[ECTOR]". It uses a writeback and write allocate on a miss scheme, and supports a configurable number of cache levels and ways, with a least-recently used replacement policy.
+
+## Dependencies
+
+g++, CMake, and the following libraries are required to compile:
+
+- cmake (tested with v3.30.3)
+- g++ (tested with v11.4.0)
+- catch2 (tested with v3.5.3)
+
+## To run
-## to compile
Generate the build directory with
`cmake -S . -B build`
@@ -20,6 +24,6 @@ then compile both the simulator and tests with
# about
-University of Massachusetts, Amherst
-CS535 -- Computer Architecture and ISA Design
+Created at the University of Massachusetts, Amherst
+CS535 -- Computer Architecture and ISA Design