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'RAM Acts Magically' a memory simulator supporting configurable cache levels and ways
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cache.h
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Author
2025-03-11
Rename read/write to read_line and write_word
bd
2025-03-11
remove operation.h and branch determined by read/write in cache load
bd
2025-03-11
read has to wait until cache has the right line from memory after eviction, ↵
Siddarth-Suresh
write only has to wait until eviction and does not care about line replacement in cache from memory
2025-03-11
Resolving conflicts
Siddarth-Suresh
2025-03-11
support for reading word, writing line to storage, dirty cache eviction, ↵
Siddarth-Suresh
cache load
2025-03-11
Write line, dirty cache eviction, cache load word/line (for future ↵
Siddarth-Suresh
multilevel cache implementation)
2025-03-10
overload << operator for dram
bd
2025-03-10
Add starter overloaded << operator for cache
bd
2025-03-10
Update cli method signatures, add some getters to cache and storage
bd
2025-03-09
cache store single test
bd
2025-03-09
Untested implementation for loading absent data into cache
bd
2025-03-09
Move do_write to dram.h, is_blocked flag
bd
2025-03-09
finish merge conflict
bd
2025-03-09
Merge remote-tracking branch 'origin/master' into bdunahu
bd
2025-03-09
Add bitset field to cache.h for keeping track of write/validity
bd
2025-03-09
Implement dram load
Siddarth-Suresh
2025-03-08
Refactor function return scheme
bd
2025-03-06
dram write (no delay, no accessor tracking
bd
2025-03-06
Storage.view method, some initial tests
bd
2025-03-05
whitespace
bd
2025-03-05
constructors + method declarations for cache, dram, reponse, storage
bd