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'RAM Acts Magically' a memory simulator supporting configurable cache levels and ways
bd
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2025-03-26
Add fetch stage implementation, tests, program loading, DTO object
bd
2025-03-24
Added gui folder with its own CMake to house GUI+main.cc
bd
2025-03-23
Remove Python, combine main files
bd
2025-03-23
Initial GUI Commit
Siddarth-Suresh
2025-03-23
Merge pull request #30 from bdunahu/bdunahu
bd
Add controller.h, implementation and tests.
2025-03-22
Remove manual clock advancing / resolution from storage devices
bd
2025-03-22
Add controller.h, implementation and tests.
bd
2025-03-21
add 'process' function to handle boilerplate on every request
bd
2025-03-21
Small cleanups to up a lot of inplementation details
bd
2025-03-21
Rewrite current cache.cc tests, add test-helper function to dram
bd
2025-03-20
Rewrite all Dram tests to use Fixture
bd
2025-03-11
Fix small issue in fetch_resource wih off by one cycle count
bd
2025-03-11
fix lots of bugs
bd
2025-03-11
Merge remote-tracking branch 'origin/master' into bdunahu
bd
2025-03-11
Rename read/write to read_line and write_word
bd
2025-03-11
remove operation.h and branch determined by read/write in cache load
bd
2025-03-11
read has to wait until cache has the right line from memory after eviction, ↵
Siddarth-Suresh
write only has to wait until eviction and does not care about line replacement in cache from memory
2025-03-11
Tests for write line in Dram, memory address wrapping implementation and tests
Siddarth-Suresh
2025-03-11
Clarify size of mem and cache in definitions, CLI print invalid tags
bd
2025-03-11
Resolving conflicts
Siddarth-Suresh
2025-03-11
support for reading word, writing line to storage, dirty cache eviction, ↵
Siddarth-Suresh
cache load
2025-03-11
Write line, dirty cache eviction, cache load word/line (for future ↵
Siddarth-Suresh
multilevel cache implementation)
2025-03-11
Remove header with unimplemented functions
bd
2025-03-11
fix namespace issues with match function
bd
2025-03-11
cli display clock cycle, parse ';' delimited commands
bd
2025-03-10
overload << operator for dram
bd
2025-03-10
before error with catch crashing with global singleton logger
bd
2025-03-10
Make logger a global singleton class
bd
2025-03-10
CLI view, clock, store, program banner
bd
2025-03-10
Add starter overloaded << operator for cache
bd
2025-03-10
Update cli method signatures, add some getters to cache and storage
bd
2025-03-09
cache store single test
bd
2025-03-09
Untested implementation for loading absent data into cache
bd
2025-03-09
Move do_write to dram.h, is_blocked flag
bd
2025-03-09
finish merge conflict
bd
2025-03-09
Merge remote-tracking branch 'origin/master' into bdunahu
bd
2025-03-09
Improve documentation in definitions.h
bd
2025-03-09
Code review comments
Siddarth-Suresh
2025-03-09
Add bitset field to cache.h for keeping track of write/validity
bd
2025-03-09
Implement dram load
Siddarth-Suresh
2025-03-08
Add get_bit_fields, which parses cache fields from a memory address
bd
2025-03-08
Remove queue in storage.h
bd
2025-03-08
Merge remote-tracking branch 'origin/master' into bdunahuer
bd
2025-03-08
enforce single unit per clock cycle, order to serve storage requests
bd
2025-03-08
Refactor function return scheme
bd
2025-03-07
Separating out CLI into a separate module
Siddarth-Suresh
2025-03-06
Allow sidedoor free access to writing memory
bd
2025-03-06
dram implement delay and conflicting request logic
bd
2025-03-06
dram write (no delay, no accessor tracking
bd
2025-03-06
Storage.view method, some initial tests
bd
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