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authorSiddarth-Suresh <65844402+Siddarth-Suresh@users.noreply.github.com>2025-04-27 00:04:53 -0400
committerSiddarth-Suresh <65844402+Siddarth-Suresh@users.noreply.github.com>2025-04-27 00:04:53 -0400
commitee4af301dfd61b21e8aa3ce04e7a77b716d65f24 (patch)
tree0a63783440d514f19af5de40e1ec6275a0c645a4
parentbd4714ae53898337a02cfcec17628eeff9d77a9c (diff)
LOADV Changes
-rw-r--r--src/id.cc6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/id.cc b/src/id.cc
index d51c70c..28a48a0 100644
--- a/src/id.cc
+++ b/src/id.cc
@@ -227,11 +227,15 @@ void ID::decode_I_type(signed int &s1)
this->status = (r1 == OK && r2 == OK && r3 == OK) ? OK : STALLED;
return;
case LOADV:
+ this->curr_instr->slot_C = s3;
s2 = GET_LS_BITS(s1, s0b);
s1 = GET_MID_BITS(s1, s0b, s1b);
- r1 = this->read_vec_guard(s1, this->curr_instr->operands.vector.slot_one);
+ // base address
+ r1 = this->read_guard(s1);
+ this->curr_instr->slot_B = s1;
r3 = this->set_vlen();
if (r1 == OK && r3 == OK)
+ // vector destination
this->write_vec_guard(s2, this->curr_instr->operands.vector.slot_two);
this->status = (r1 == OK && r3 == OK) ? OK : STALLED;
return;