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| author | Siddarth Suresh <155843085+SiddarthSuresh98@users.noreply.github.com> | 2025-04-28 21:49:25 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-28 21:49:25 -0400 |
| commit | 32a1762b3b9091f6e2d553601f3e3a3a5d87b889 (patch) | |
| tree | cb12daab120a8298d5e78219602fded822bdd671 /inc/controller.h | |
| parent | 9e7debd7bff14893f2722c37f42d9c6b70fbdcbf (diff) | |
| parent | 930ec733e988c4996918065b4656f0508c6e2df6 (diff) | |
Merge pull request #76 from bdunahu/bdunahu
Fix bug with pipeline blockage, swap DRAM delay to 100
Diffstat (limited to 'inc/controller.h')
| -rw-r--r-- | inc/controller.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/inc/controller.h b/inc/controller.h index cd59fc8..d8f6439 100644 --- a/inc/controller.h +++ b/inc/controller.h @@ -41,7 +41,7 @@ class Controller : public Stage * Direct the simulator to run for `number` clock cycles. * @param the number of clock cycles to run for. */ - void run_for(int number); + void run_for(long number); /** * @return the current clock cycle. */ |