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authorbd <bdunahu@operationnull.com>2025-04-28 18:24:49 -0400
committerbd <bdunahu@operationnull.com>2025-04-28 18:24:49 -0400
commit930ec733e988c4996918065b4656f0508c6e2df6 (patch)
treecb12daab120a8298d5e78219602fded822bdd671 /inc/pipe_spec.h
parent9e7debd7bff14893f2722c37f42d9c6b70fbdcbf (diff)
Fix bug with pipeline blockage, swap DRAM delay to 100
Diffstat (limited to 'inc/pipe_spec.h')
-rw-r--r--inc/pipe_spec.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/inc/pipe_spec.h b/inc/pipe_spec.h
index d8153af..ad8a7fc 100644
--- a/inc/pipe_spec.h
+++ b/inc/pipe_spec.h
@@ -73,12 +73,12 @@
/**
* The delay on DRAM objects.
*/
-#define DRAM_DELAY 10
+#define DRAM_DELAY 100
/**
- * The (base) on cache objects.
+ * The difference in delays between two adjacent cache levels.
*/
-#define CACHE_DELAY 1
+#define CACHE_DELAY_SCALE 1
#define VECTOR_MEM_DELAY 10