Merge pull request #37 from bdunahu/bdunahu

Instr, InstrDTO gets/sets, other structures required for decode

-- tests as we move forward
-- base classes
-- decode stage implemented

1 files changed, 48 insertions, 10 deletions

diff --git a/inc/stage.h b/inc/stage.h
index ac810a9..19e3896 100644
--- a/inc/stage.h
+++ b/inc/stage.h
@@ -1,10 +1,13 @@
 #ifndef STAGE_H
 #define STAGE_H
+#include "accessor.h"
 #include "definitions.h"
 #include "instrDTO.h"
 #include "response.h"
 #include "storage.h"
 #include <array>
+#include <deque>
+#include <memory>
 
 class Stage
 {
@@ -15,29 +18,47 @@ class Stage
 	 * @return A newly allocated stage object.
 	 */
 	Stage(Stage *next);
-	virtual ~Stage() = default;
+	virtual ~Stage();
 	/**
 	 * Advances this stage by a single clock cycle.
-	 * @param a DTO object containing various information about an instruction
-	 * moving through the pipeline.
-	 * @return a response, indicating whether this pipeline stage is stalled,
+	 * @param a DTO object containing the next instruction to be processed.
+	 * @param a response, indicating whether or not the parent pipe stage is
+	 * ready to accept a new instruction object next cycle.
+	 * @return a response, indicating whether this pipeline stage is stalling,
 	 * busy, or done.
 	 */
-	virtual Response advance(InstrDTO &i) = 0;
+	virtual Response advance(InstrDTO &next_instr, Response p) = 0;
 
   protected:
 	/**
+	 * Helper for `check_out`.
+	 * Returns true if r are not checked out, false otherwise.
+	 * @param a list of register numbers.
+	 * @return true if registers are not in checked_out, false otherwise.
+	 */
+	bool is_checked_out(signed int r);
+	/**
+	 * Returns the value of the register corresponding to `v`.
+	 * @param the register number.
+	 * @return the value in the associated register.
+	 */
+	signed int dereference_register(signed int v);
+	/**
+	 * The name of the pipeline stage.
+	 */
+	Accessor id;
+	/**
 	 * The shared pool of general-purpose integer registers.
 	 */
-	static std::array<int, GPR_NUM> gprs;
+	static std::array<signed int, GPR_NUM> gprs;
 	/**
-	 * The address of the currently executing instruction.
+	 * The shared pool of general-purpose vector registers.
 	 */
-	static int pc;
+	static std::array<signed int, V_NUM> vrs;
 	/**
-	 * A pointer to the next stage in the pipeline.
+	 * The address of the currently executing instruction.
 	 */
-	Stage *next;
+	static unsigned int pc;
 	/**
 	 * A pointer to the top-level storage device.
 	 */
@@ -50,6 +71,23 @@ class Stage
 	 * The current clock cycle.
 	 */
 	static int clock_cycle;
+	// TODO fix this comment after writeback stage
+	/**
+	 * The set of registers currently checked out.
+	 */
+	static std::deque<signed int> checked_out;
+	/**
+	 * A pointer to the next stage in the pipeline.
+	 */
+	Stage *next;
+	/**
+	 * A pointer to the current instruction this stage is processing.
+	 */
+	std::unique_ptr<InstrDTO> curr_instr;
+	/**
+	 * The current status of this stage.
+	 */
+	Response status;
 };
 
 #endif /* STAGE_H_INCLUDED */