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author | Siddarth Suresh <155843085+SiddarthSuresh98@users.noreply.github.com> | 2025-05-11 23:39:06 -0400 |
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committer | GitHub <noreply@github.com> | 2025-05-11 23:39:06 -0400 |
commit | f02bea04284d33a2d014f636baa6a861b73f6c41 (patch) | |
tree | ce89a55af60b01f6b4129d7539d07c08bfaa1b9a /inc/wb.h | |
parent | a35eb451889f0efa99ff7fe1c0a3a76afd5e7ad5 (diff) | |
parent | 43588597069587f6846a7d64a1957435bec5429d (diff) |
Replace LOADV, STOREV, with strided load (SRDL), strided store (SRDS), add vector rotate (ROTV)
Diffstat (limited to 'inc/wb.h')
-rw-r--r-- | inc/wb.h | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -51,7 +51,8 @@ class WB : public Stage * @return the vector register to be stored, obtained by copying the * unfilled elements in the destination register to the source. This is * required to ensure what is written back only changes VECTOR_LENGTH number - * of elements. + * of elements. Correctly handles zeroing out ALU operations if the VECTOR + * LENGTH number is zero. */ std::array<signed int, V_R_LIMIT> copy_extra_vector_elements(); }; |