summaryrefslogtreecommitdiff
path: root/src/sim/stage.cc
diff options
context:
space:
mode:
authorbd <bdunahu@operationnull.com>2025-03-30 12:33:25 -0400
committerbd <bdunahu@operationnull.com>2025-03-30 12:33:25 -0400
commit6557e7e623140871968776429d241570002a65f5 (patch)
tree420c2aced8e008708ea951edf36608e0bc5d4e2c /src/sim/stage.cc
parent8e56373a5436852fe9c7934e03d7b57493625003 (diff)
Setting condition code register, overflow guard
Diffstat (limited to 'src/sim/stage.cc')
-rw-r--r--src/sim/stage.cc12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/sim/stage.cc b/src/sim/stage.cc
index 62a7fd6..d8c882a 100644
--- a/src/sim/stage.cc
+++ b/src/sim/stage.cc
@@ -21,6 +21,18 @@ Storage *Stage::storage;
bool Stage::is_pipelined;
int Stage::clock_cycle;
+void Stage::set_condition(CC c, bool v)
+{
+ if (v)
+ this->gprs[3] = this->gprs[3] & 1 << c;
+ else
+ this->gprs[3] = this->gprs[3] & ~(1 << c);
+}
+
+bool Stage::get_condition(CC c) {
+ return (this->gprs[3] >> c) & 1;
+}
+
signed int Stage::dereference_register(signed int v)
{
signed int r;