Replaced STOREV with LOADV

3 files changed, 46 insertions, 50 deletions

diff --git a/src/ex.cc b/src/ex.cc
index 56a59d7..3328cbe 100644
--- a/src/ex.cc
+++ b/src/ex.cc
@@ -243,18 +243,14 @@ void EX::handle_vector_operations(
 void EX::handle_i_vector_operations(signed int &s1, signed int s2, Mnemonic m)
 {
 	switch (m) {
-	case LOADV:
-	case STOREV:
-		s1 = s1 + s2;
-		break;
-
-	case RET:
-	case NOP:
-		break;
+	// case SRDL:
+	// case SRDS:
+	// 	s1 = s1 + s2;
+	// 	break;
 
 	default:
 		throw std::invalid_argument("handle_i_vector_operations did not "
-									"receive a LOADV or STOREV operation!");
+									"receive a SRDL or SRDS operation!");
 	}
 }
 
diff --git a/src/id.cc b/src/id.cc
index 85637a6..371e3b7 100644
--- a/src/id.cc
+++ b/src/id.cc
@@ -164,35 +164,35 @@ void ID::decode_I_type(signed int &s1)
 		this->curr_instr->operands.integer.slot_two = s2;
 		this->status = (r1 == OK && r2 == OK) ? OK : STALLED;
 		return;
-	case STOREV:
-		this->curr_instr->operands.i_vector.slot_two = s3;
-		s2 = GET_MID_BITS(s1, s0b, s1b);
-		s1 = GET_LS_BITS(s1, s0b);
+	// case SRDS:
+	// 	this->curr_instr->operands.i_vector.slot_two = s3;
+	// 	s2 = GET_MID_BITS(s1, s0b, s1b);
+	// 	s1 = GET_LS_BITS(s1, s0b);
 
-		// base address
-		r1 = this->read_guard<signed int>(s1, s1);
-		this->curr_instr->operands.i_vector.slot_one = s1;
-		// vector value to be stored
-		r2 = this->read_guard<std::array<signed int, V_R_LIMIT>>(
-			s2, this->curr_instr->operands.i_vector.slot_three);
-		r3 = this->set_vlen();
+	// 	// base address
+	// 	r1 = this->read_guard<signed int>(s1, s1);
+	// 	this->curr_instr->operands.i_vector.slot_one = s1;
+	// 	// vector value to be stored
+	// 	r2 = this->read_guard<std::array<signed int, V_R_LIMIT>>(
+	// 		s2, this->curr_instr->operands.i_vector.slot_three);
+	// 	r3 = this->set_vlen();
 
-		this->status = (r1 == OK && r2 == OK && r3 == OK) ? OK : STALLED;
-		return;
-	case LOADV:
-		this->curr_instr->operands.i_vector.slot_two = s3;
-		s2 = GET_LS_BITS(s1, s0b);
-		s1 = GET_MID_BITS(s1, s0b, s1b);
-		// base address
-		r1 = this->read_guard<signed int>(s1, s1);
-		this->curr_instr->operands.i_vector.slot_one = s1;
-		r3 = this->set_vlen();
-		if (r1 == OK && r3 == OK)
-			// vector destination
-			this->curr_instr->operands.i_vector.slot_three =
-				this->write_guard<std::array<signed int, V_R_LIMIT>>(s2);
-		this->status = (r1 == OK && r3 == OK) ? OK : STALLED;
-		return;
+	// 	this->status = (r1 == OK && r2 == OK && r3 == OK) ? OK : STALLED;
+	// 	return;
+	// case SRDL:
+	// 	this->curr_instr->operands.i_vector.slot_two = s3;
+	// 	s2 = GET_LS_BITS(s1, s0b);
+	// 	s1 = GET_MID_BITS(s1, s0b, s1b);
+	// 	// base address
+	// 	r1 = this->read_guard<signed int>(s1, s1);
+	// 	this->curr_instr->operands.i_vector.slot_one = s1;
+	// 	r3 = this->set_vlen();
+	// 	if (r1 == OK && r3 == OK)
+	// 		// vector destination
+	// 		this->curr_instr->operands.i_vector.slot_three =
+	// 			this->write_guard<std::array<signed int, V_R_LIMIT>>(s2);
+	// 	this->status = (r1 == OK && r3 == OK) ? OK : STALLED;
+	// 	return;
 	case LOAD:
 		this->curr_instr->operands.integer.slot_three = s3;
 		s2 = GET_LS_BITS(s1, s0b);
diff --git a/src/instr.cc b/src/instr.cc
index ee2d37f..98028fc 100644
--- a/src/instr.cc
+++ b/src/instr.cc
@@ -23,26 +23,26 @@
 namespace instr
 {
 const std::unordered_map<unsigned int, Mnemonic> mnemonic_map = {
-	{0b0000100, ADD},	 {0b0001000, SUB},	 {0b0001100, MUL},
-	{0b0010000, QUOT},	 {0b0010100, REM},	 {0b0011000, SFTR},
-	{0b0011100, SFTL},	 {0b0100000, AND},	 {0b0100100, OR},
-	{0b0101000, NOT},	 {0b0101100, XOR},	 {0b0110000, ADDV},
-	{0b0110100, SUBV},	 {0b0111000, MULV},	 {0b0111100, DIVV},
-	{0b1000000, CMP},	 {0b1000100, CEV},	 {0b000101, LOAD},
-	{0b001001, LOADV},	 {0b0001101, ADDI},	 {0b0010001, SUBI},
-	{0b0010101, SFTRI},	 {0b0011001, SFTLI}, {0b0011101, ANDI},
-	{0b0100001, ORI},	 {0b0100101, XORI},	 {0b0101001, STORE},
-	{0b0101101, STOREV}, {0b0000110, JMP},	 {0b0001010, JRL},
-	{0b0001110, JAL},	 {0b0010010, BEQ},	 {0b0010110, BGT},
-	{0b0011010, BUF},	 {0b0011110, BOF},	 {0b0100010, PUSH},
-	{0b0100110, POP},	 {0b0101010, RET},
+	{0b0000100, ADD},	{0b0001000, SUB},	{0b0001100, MUL},
+	{0b0010000, QUOT},	{0b0010100, REM},	{0b0011000, SFTR},
+	{0b0011100, SFTL},	{0b0100000, AND},	{0b0100100, OR},
+	{0b0101000, NOT},	{0b0101100, XOR},	{0b0110000, ADDV},
+	{0b0110100, SUBV},	{0b0111000, MULV},	{0b0111100, DIVV},
+	{0b1000000, CMP},	{0b1000100, CEV},	{0b1001000, SRDL},
+	{0b1001100, SRDS},	{0b000101, LOAD},	{0b0001001, ADDI},
+	{0b0001101, SUBI},	{0b0010001, SFTRI}, {0b0010101, SFTLI},
+	{0b0011001, ANDI},	{0b0011101, ORI},	{0b0100001, XORI},
+	{0b0100101, STORE}, {0b0000110, JMP},	{0b0001010, JRL},
+	{0b0001110, JAL},	{0b0010010, BEQ},	{0b0010110, BGT},
+	{0b0011010, BUF},	{0b0011110, BOF},	{0b0100010, PUSH},
+	{0b0100110, POP},	{0b0101010, RET},
 };
 
 FieldType get_field_types(Mnemonic m)
 {
 	if (m == ADDV || m == SUBV || m == MULV || m == DIVV || m == CEV) {
 		return R_VECT;
-	} else if (m == STOREV || m == LOADV) {
+	} else if (m == SRDL || m == SRDS) {
 		return I_VECT;
 	} else {
 		return SI_INT;