Add ROTV instruction

3 files changed, 23 insertions, 12 deletions

diff --git a/src/ex.cc b/src/ex.cc
index 22cd092..f36ea4b 100644
--- a/src/ex.cc
+++ b/src/ex.cc
@@ -249,6 +249,13 @@ void EX::handle_s_vector_operations(
 	unsigned int i, inc1, inc2;
 
 	switch (m) {
+	case ROTV:
+		s2 = s2 % v_len;
+		if (s2 < 0)
+			s2 += v_len;
+
+		std::rotate(s1.begin(), s1.begin() + s2, s1.begin() + v_len);
+		break;
 	case SRDL:
 	case SRDS:
 		inc1 = s1[0];
@@ -286,7 +293,6 @@ void EX::advance_helper()
 		handle_s_vector_operations(
 			this->curr_instr->operands.s_vector.slot_one,
 			this->curr_instr->operands.s_vector.slot_two, m, v_len_or_pc);
-		printArray(this->curr_instr->operands.s_vector.slot_three);
 	}
 
 	this->status = OK;
diff --git a/src/id.cc b/src/id.cc
index 9547486..58bde6b 100644
--- a/src/id.cc
+++ b/src/id.cc
@@ -99,25 +99,29 @@ void ID::decode_R_type(signed int &s1)
 	s2 = GET_MID_BITS(s1, s0b, s1b);
 	s1 = GET_LS_BITS(s1, s0b);
 
-	if (this->curr_instr->type == SI_INT) {
+	switch (this->curr_instr->type) {
+	case SI_INT:
 		r1 = this->read_guard<signed int>(
 			s1, this->curr_instr->operands.integer.slot_one);
 		r2 = this->read_guard<signed int>(
 			s2, this->curr_instr->operands.integer.slot_two);
 		r3 = OK;
-	} else if (this->curr_instr->type == R_VECT) {
+		break;
+	case R_VECT:
 		r1 = this->read_guard<std::array<signed int, V_R_LIMIT>>(
 			s1, this->curr_instr->operands.vector.slot_one);
 		r2 = this->read_guard<std::array<signed int, V_R_LIMIT>>(
 			s2, this->curr_instr->operands.vector.slot_two);
 		r3 = this->set_vlen();
-	} else {
+		break;
+	case S_VECT:
 		// store the second field in s1, to keep execute+mem consistent
 		r1 = this->read_guard<std::array<signed int, V_R_LIMIT>>(
 			s2, this->curr_instr->operands.s_vector.slot_one);
 		r2 = this->read_guard<signed int>(
 			s1, this->curr_instr->operands.s_vector.slot_two);
 		r3 = this->set_vlen();
+		break;
 	}
 
 	this->status = (r1 == OK && r2 == OK && r3 == OK) ? OK : STALLED;
@@ -134,6 +138,7 @@ void ID::decode_R_type(signed int &s1)
 			this->curr_instr->operands.vector.slot_three =
 				this->write_guard<std::array<signed int, V_R_LIMIT>>(s3);
 			break;
+		case ROTV:
 		case SRDL:
 			this->curr_instr->operands.s_vector.slot_three =
 				this->write_guard<std::array<signed int, V_R_LIMIT>>(s3);
diff --git a/src/instr.cc b/src/instr.cc
index 271fc99..a638a38 100644
--- a/src/instr.cc
+++ b/src/instr.cc
@@ -29,20 +29,20 @@ const std::unordered_map<unsigned int, Mnemonic> mnemonic_map = {
 	{0b0101000, NOT},	{0b0101100, XOR},	{0b0110000, ADDV},
 	{0b0110100, SUBV},	{0b0111000, MULV},	{0b0111100, DIVV},
 	{0b1000000, CMP},	{0b1000100, CEV},	{0b1001000, SRDL},
-	{0b1001100, SRDS},	{0b000101, LOAD},	{0b0001001, ADDI},
-	{0b0001101, SUBI},	{0b0010001, SFTRI}, {0b0010101, SFTLI},
-	{0b0011001, ANDI},	{0b0011101, ORI},	{0b0100001, XORI},
-	{0b0100101, STORE}, {0b0000110, JMP},	{0b0001010, JRL},
-	{0b0001110, JAL},	{0b0010010, BEQ},	{0b0010110, BGT},
-	{0b0011010, BUF},	{0b0011110, BOF},	{0b0100010, PUSH},
-	{0b0100110, POP},	{0b0101010, RET},
+	{0b1001100, SRDS},	{0b1010000, ROTV},	{0b000101, LOAD},
+	{0b0001001, ADDI},	{0b0001101, SUBI},	{0b0010001, SFTRI},
+	{0b0010101, SFTLI}, {0b0011001, ANDI},	{0b0011101, ORI},
+	{0b0100001, XORI},	{0b0100101, STORE}, {0b0000110, JMP},
+	{0b0001010, JRL},	{0b0001110, JAL},	{0b0010010, BEQ},
+	{0b0010110, BGT},	{0b0011010, BUF},	{0b0011110, BOF},
+	{0b0100010, PUSH},	{0b0100110, POP},	{0b0101010, RET},
 };
 
 FieldType get_field_types(Mnemonic m)
 {
 	if (m == ADDV || m == SUBV || m == MULV || m == DIVV || m == CEV) {
 		return R_VECT;
-	} else if (m == SRDL || m == SRDS) {
+	} else if (m == SRDL || m == SRDS || m == ROTV) {
 		return S_VECT;
 	} else {
 		return SI_INT;