get_instr_fields return mnemonic rather than opcode and type

4 files changed, 84 insertions, 55 deletions

diff --git a/src/cli/cli.cc b/src/cli/cli.cc
index 022b266..58575cb 100644
--- a/src/cli/cli.cc
+++ b/src/cli/cli.cc
@@ -3,6 +3,7 @@
 #include "definitions.h"
 #include "dram.h"
 #include "response.h"
+#include "accessor.h"
 #include "utils.h"
 #include <iostream>
 
@@ -43,6 +44,7 @@ Cli::Cli()
 	};
 
 	commands['r'] = [this](std::vector<std::string> args) {
+		(void)args;
 		reset();
 		return;
 	};
@@ -61,6 +63,7 @@ Cli::Cli()
 	};
 
 	commands['h'] = [this](std::vector<std::string> args) {
+		(void)args;
 		help();
 		return;
 	};
diff --git a/src/sim/id.cc b/src/sim/id.cc
index 65acef5..c6e42d5 100644
--- a/src/sim/id.cc
+++ b/src/sim/id.cc
@@ -1,5 +1,6 @@
 #include "id.h"
 #include "accessor.h"
+#include "instr.h"
 #include "instrDTO.h"
 #include "logger.h"
 #include "response.h"
@@ -12,54 +13,70 @@ ID::ID(Stage *stage) : Stage(stage) { this->id = DCDE; }
 
 Response ID::advance(InstrDTO &i) { Response r; }
 
+// TODO this function is ugly
 void ID::get_instr_fields(
-	signed int &s1,
-	signed int &s2,
-	signed int &s3,
-	unsigned int &type,
-	unsigned int &opcode)
+	signed int &s1, signed int &s2, signed int &s3, Mnemonic &m)
 {
-	// unsigned int &opcode;
-	int opcode_bits;
-
-	type = GET_LS_BITS(s1, TYPE_SIZE);
-	opcode_bits = (type == 0b0) ? R_OPCODE_SIZE : OPCODE_SIZE;
+	unsigned int type, s0b, s1b, s2b;
+	this->split_instr(s1, type, m);
 
+	// define the parsing bounds
+	s0b = REG_SIZE;
 	switch (type) {
-	case 0:
+	case 0b00:
 		// R-TYPE
-		opcode += GET_MID_BITS(s1, TYPE_SIZE, TYPE_SIZE + opcode_bits);
-		s3 = GET_MID_BITS(
-			s1, TYPE_SIZE + opcode_bits + (REG_SIZE * 2),
-			TYPE_SIZE + opcode_bits + (REG_SIZE * 3));
-		s2 = GET_MID_BITS(
-			s1, TYPE_SIZE + opcode_bits + REG_SIZE,
-			TYPE_SIZE + opcode_bits + (REG_SIZE * 2));
-		s1 = GET_MID_BITS(
-			s1, TYPE_SIZE + opcode_bits,
-			TYPE_SIZE + opcode_bits + REG_SIZE);
+		s1b = s0b + REG_SIZE;
+		s2b = s1b + REG_SIZE;
 		break;
-	case 1:
+	case 0b01:
 		// I-TYPE
-		opcode = GET_MID_BITS(s1, TYPE_SIZE, TYPE_SIZE + opcode_bits);
-		s3 = GET_MID_BITS(
-			s1, TYPE_SIZE + opcode_bits + (REG_SIZE * 2), WORD_SPEC);
-		s2 = GET_MID_BITS(
-			s1, TYPE_SIZE + opcode_bits + REG_SIZE,
-			TYPE_SIZE + opcode_bits + (REG_SIZE * 2));
-		s1 = GET_MID_BITS(
-			s1, TYPE_SIZE + opcode_bits, TYPE_SIZE + opcode_bits + REG_SIZE);
+		s1b = s0b + REG_SIZE;
+		s2b = WORD_SPEC;
 		break;
-	case 2:
+	case 0b10:
 		// J-TYPE
-		opcode = GET_MID_BITS(s1, TYPE_SIZE, TYPE_SIZE + opcode_bits);
-		s2 = GET_MID_BITS(s1, TYPE_SIZE + OPCODE_SIZE + REG_SIZE, WORD_SPEC);
-		s1 = GET_MID_BITS(
-			s1, TYPE_SIZE + OPCODE_SIZE, TYPE_SIZE + OPCODE_SIZE + REG_SIZE);
-		break;
-	default:
-		global_log->log(
-			DEBUG,
-			string_format("%s returning invalid type: %d", __FUNCTION__, type));
+		s1b = WORD_SPEC;
 	}
+
+	if (type != 0b10)
+		s3 = GET_MID_BITS(s1, s1b, s2b);
+
+	s2 = GET_MID_BITS(s1, s0b, s1b);
+	s1 = GET_LS_BITS(s1, s0b);
+}
+
+void ID::split_instr(signed int &raw, unsigned int &type, Mnemonic &m)
+{
+	unsigned int opcode, opcode_size;
+
+	type = GET_LS_BITS(raw, TYPE_SIZE);
+	opcode_size = (type == 0b0) ? R_OPCODE_SIZE : OPCODE_SIZE;
+	opcode = GET_MID_BITS(raw, TYPE_SIZE, TYPE_SIZE + opcode_size);
+	try {
+		m = instr::mnemonic_map.at((opcode << 2) + type);
+	} catch (std::out_of_range const &) {
+		m = NOP;
+	}
+
+	raw = (unsigned int)raw >> (TYPE_SIZE + opcode_size);
+}
+
+Response ID::dereference_register(signed int &v)
+{
+	Response r;
+	r = OK;
+
+	if (v < 0 || v >= GPR_NUM + V_NUM) {
+		global_log->log(
+			ERROR, string_format(
+					   "instruction tried to access register %d, which does "
+					   "not exist",
+					   v));
+		exit(EXIT_FAILURE);
+	} else if (v >= GPR_NUM)
+		v = this->vrs[v % GPR_NUM];
+	else
+		v = this->gprs[v];
+
+	return r;
 }
diff --git a/src/sim/instr.cc b/src/sim/instr.cc
index 50aa71d..08edf5e 100644
--- a/src/sim/instr.cc
+++ b/src/sim/instr.cc
@@ -1,6 +1,7 @@
 #include "instr.h"
 #include <functional>
 #include <map>
+#include <unordered_map>
 
 // clang-format off
 #define INIT_INSTRUCTION(mnemonic, body) \
@@ -12,7 +13,7 @@
 namespace instr
 {
 // clang-format off
-const std::map<Mnemonic, std::function<void(signed int &s1, signed int &s2, signed int &s3)>>
+const std::unordered_map<Mnemonic, std::function<void(signed int &s1, signed int &s2, signed int &s3)>>
 	// clang-format on
 	instr_map = {
 
@@ -20,26 +21,33 @@ const std::map<Mnemonic, std::function<void(signed int &s1, signed int &s2, sign
 		// TODO these need to be WRAPPED with a function that sets overflow.
 		// future note to self, if these are more than 2 lines each, you're
 		// doing it wrong
-		INIT_INSTRUCTION(ADD, s3 = s1 + s2),
-		INIT_INSTRUCTION(SUB, s3 = s1 - s2),
+		INIT_INSTRUCTION(ADD, s3 = s1 + s2;),
+		INIT_INSTRUCTION(SUB, s3 = s1 - s2;),
 
 		/* I type instructions */
 
 		/* J type instructions */
+
+		/* NOP */
+		INIT_INSTRUCTION(NOP, (void)s3; (void)s2; (void)s1;),
+
 };
 
-const std::map<unsigned int, Mnemonic> mnemonic_map = {
-	{0b0000100, ADD},  {0b0001000, SUB},  {0b0001100, MUL},	 {0b0010000, QUOT},
-	{0b0010100, REM},  {0b0011000, SFTR}, {0b0011100, SFTL}, {0b0100000, AND},
-	{0b0100100, OR},   {0b0101000, NOT},  {0b0101100, XOR},	 {0b0110000, ADDV},
-	{0b0110100, SUBV}, {0b0111000, MULV}, {0b0111100, DIVV}, {0b1000000, CMP},
-	{0b1000100, CEV},  {0b000101, LOAD},  {0b001001, LOADV}, {0b001101, ADDI},
-	{0b010001, SUBI},  {0b010101, SFTRI}, {0b011101, SFTLI}, {0b100001, ANDI},
-	{0b100101, ORI},   {0b101001, XORI},  {0b101101, STORE}, {0b110001, STOREV},
-	{0b000101, CEV},   {0b000101, LOAD},  {0b001001, LOADV}, {0b001001, LOADV},
-	{0b000110, JMP},   {0b001010, JRL},	  {0b001110, JAL},	 {0b010010, BEQ},
-	{0b010110, BGT},   {0b011010, BUF},	  {0b011110, BOF},	 {0b100010, PUSH},
-	{0b100110, POP},
+const std::unordered_map<unsigned int, Mnemonic> mnemonic_map = {
+	{0b0000100, ADD},	 {0b0001000, SUB},	 {0b0001100, MUL},
+	{0b0010000, QUOT},	 {0b0010100, REM},	 {0b0011000, SFTR},
+	{0b0011100, SFTL},	 {0b0100000, AND},	 {0b0100100, OR},
+	{0b0101000, NOT},	 {0b0101100, XOR},	 {0b0110000, ADDV},
+	{0b0110100, SUBV},	 {0b0111000, MULV},	 {0b0111100, DIVV},
+	{0b1000000, CMP},	 {0b1000100, CEV},	 {0b000101, LOAD},
+	{0b001001, LOADV},	 {0b0001101, ADDI},	 {0b0010001, SUBI},
+	{0b0010101, SFTRI},	 {0b0011101, SFTLI}, {0b0100001, ANDI},
+	{0b0100101, ORI},	 {0b0101001, XORI},	 {0b0101101, STORE},
+	{0b0110001, STOREV}, {0b0000101, CEV},	 {0b0000101, LOAD},
+	{0b0001001, LOADV},	 {0b0001001, LOADV}, {0b0000110, JMP},
+	{0b0001010, JRL},	 {0b0001110, JAL},	 {0b0010010, BEQ},
+	{0b0010110, BGT},	 {0b0011010, BUF},	 {0b0011110, BOF},
+	{0b0100010, PUSH},	 {0b0100110, POP},
 
 };
 } // namespace instr
diff --git a/src/sim/stage.cc b/src/sim/stage.cc
index 6599298..560cc41 100644
--- a/src/sim/stage.cc
+++ b/src/sim/stage.cc
@@ -5,6 +5,7 @@ Stage::Stage(Stage *next) {
 }
 
 std::array<int, GPR_NUM> Stage::gprs;
+std::array<int, V_NUM> Stage::vrs;
 unsigned int Stage::pc;
 Storage *Stage::storage;
 bool Stage::is_pipelined;