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-rw-r--r--src/sim/controller.cc38
-rw-r--r--src/sim/stage.cc5
-rw-r--r--src/storage/cache.cc1
3 files changed, 43 insertions, 1 deletions
diff --git a/src/sim/controller.cc b/src/sim/controller.cc
new file mode 100644
index 0000000..8d48dc9
--- /dev/null
+++ b/src/sim/controller.cc
@@ -0,0 +1,38 @@
+#include "controller.h"
+#include "storage.h"
+
+Controller::Controller(Storage *storage, bool is_pipelined)
+{
+ this->clock_cycle = 0;
+ this->storage = storage;
+ this->is_pipelined = is_pipelined;
+ this->pc = 0x0;
+ this->gprs = {0};
+
+ // setup the other pipeline stages
+ this->next = nullptr;
+}
+
+Controller::~Controller() { ; }
+
+void Controller::run_for(int number)
+{
+ int i;
+ for (i = 0; i < number; ++i) {
+ this->advance();
+ }
+}
+
+int Controller::get_clock_cycle() { return this->clock_cycle; }
+
+std::array<int, GPR_NUM> Controller::get_gprs() {
+ return this->gprs;
+}
+
+int Controller::get_pc() { return this->pc; }
+
+void Controller::advance() {
+ ;
+ // this->next->advance()
+ ++this->clock_cycle;
+}
diff --git a/src/sim/stage.cc b/src/sim/stage.cc
new file mode 100644
index 0000000..7d3a678
--- /dev/null
+++ b/src/sim/stage.cc
@@ -0,0 +1,5 @@
+#include "stage.h"
+
+std::array<int, GPR_NUM> Stage::gprs;
+int Stage::pc;
+Storage *Stage::storage;
diff --git a/src/storage/cache.cc b/src/storage/cache.cc
index d96efe2..dccab47 100644
--- a/src/storage/cache.cc
+++ b/src/storage/cache.cc
@@ -3,7 +3,6 @@
#include "response.h"
#include "utils.h"
#include <bits/stdc++.h>
-#include <bitset>
#include <iostream>
#include <iterator>