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RISC-VECTOR.git
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A simulator for the custom RISC-V[ECTOR] ISA written in C++
bd
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Commit message (
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Author
2025-04-17
Add option to turn off pipeline
bd
2025-04-17
Fix the tests which could be fixed, delete others
bd
2025-04-17
HALT instruction... but it voids future stages' instructions
bd
2025-04-17
Functioning PUSH/POP
bd
2025-04-17
The pipeline says some things and there are numbers
bd
2025-04-17
Swap the source and destination registers for LOAD, final fix
bd
2025-04-17
Swap the source and destination registers for LOAD, final fix
bd
2025-04-17
Keep track of checked out in DTO to simplify wb cond logic (bug)
bd
2025-04-16
Fix instruction opcode numbering issue, use assembler's output
bd
2025-04-16
Fix a bug related to parsing immediates in decode
bd
2025-04-16
Partial fixes for changes in DRAM/Cache, including uncovered bug
bd
2025-04-16
Merge pull request #51 from bdunahu/dev-sid
bd
2025-04-15
Added pipeline to GUI
Siddarth-Suresh
2025-04-12
Merge pull request #50 from bdunahu/bdunahu
Siddarth Suresh
2025-04-12
Add pipe_spec.h
bd
2025-04-12
Delete some more storage-only files
bd
2025-04-11
Merge remote-tracking branch 'origin/master' into bdunahu
bd
2025-04-11
Move storage to a separate git repository.
bd
2025-04-10
Update README.md
Siddarth Suresh
2025-04-02
Merge pull request #46 from bdunahu/bdunahu
bd
2025-04-02
Last fix to demo program
bd
2025-04-01
Fix bug with decode pushing checked_out when delayed with RAW
bd
2025-04-01
Merge remote-tracking branch 'origin/master' into bdunahu
bd
2025-04-01
Finish adding initial tests for full pipeline
bd
2025-04-01
Merge pull request #47 from bdunahu/dev-sid
Siddarth Suresh
2025-04-01
GUI and controller on separate threads
Siddarth-Suresh
2025-04-01
Lots of fixes and tests
bd
2025-04-01
Fix a lot of pipeline bugs
bd
2025-04-01
Ensure all stages only do work if they are not 'OK'
bd
2025-03-31
Merge remote-tracking branch 'origin/dev-sid' into bdunahu
bd
2025-03-31
Partial commit before merge
bd
2025-04-01
Merge pull request #45 from bdunahu/dev-sid
bd
2025-03-31
CR Comments
Siddarth-Suresh
2025-03-31
MEM WB stage
Siddarth-Suresh
2025-03-30
Merge pull request #43 from bdunahu/bdunahu
Siddarth Suresh
2025-03-30
Sanity check for pipeline up to exe
bd
2025-03-30
Merge pull request #42 from bdunahu/bdunahu
Siddarth Suresh
2025-03-30
Ensure type-I instruction could use S3 as displacement
bd
2025-03-30
Implementation and tests for J types
bd
2025-03-30
All I-type instructions
bd
2025-03-30
Add tests for EX
bd
2025-03-30
Merge pull request #41 from bdunahu/bdunahu
Siddarth Suresh
2025-03-30
Free everything I allocated :)
bd
2025-03-30
Add mock stage, proper decode tests
bd
2025-03-30
Merge pull request #40 from bdunahu/bdunahu
Siddarth Suresh
2025-03-30
untested ALU type R operations
bd
2025-03-30
Setting condition code register, overflow guard
bd
2025-03-30
Minor simplification to API between pipeline components
bd
2025-03-29
Fix issue with uninitialized DRAM in ID.cc tests
bd
2025-03-29
Quick fix to fix compile-error
bd
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