| Age | Commit message (Expand) | Author |
|---|---|---|
| 2025-04-17 | The pipeline says some things and there are numbers | bd |
| 2025-04-17 | Keep track of checked out in DTO to simplify wb cond logic (bug) | bd |
| 2025-04-16 | Fix instruction opcode numbering issue, use assembler's output | bd |
| 2025-04-16 | Partial fixes for changes in DRAM/Cache, including uncovered bug | bd |
| 2025-04-15 | Added pipeline to GUI | Siddarth-Suresh |
| 2025-04-02 | Last fix to demo program | bd |
| 2025-04-01 | Fix bug with decode pushing checked_out when delayed with RAW | bd |
| 2025-04-01 | GUI and controller on separate threads | Siddarth-Suresh |
 |
index : RISC-VECTOR.git | |
| A simulator for the custom RISC-V[ECTOR] ISA written in C++ | bd |
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