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RISC-VECTOR.git
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A simulator for the custom RISC-V[ECTOR] ISA written in C++
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worker.cc
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Commit message (
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Author
2025-04-18
Remove/comment out a lot of code in charge of loading
bd
2025-04-18
Use a slider for step amount
bd
2025-04-18
Remove run_steps button
bd
2025-04-18
further changes to initialize
Siddarth-Suresh
2025-04-18
initialization from GUI
Siddarth-Suresh
2025-04-17
Fix byte order
bd
2025-04-17
Merge remote-tracking branch 'origin/bdunahu' into dev-sid
bd
2025-04-17
cache size change as needed
Siddarth-Suresh
2025-04-17
Loading binary program into dram
Siddarth-Suresh
2025-04-17
Add option to turn off pipeline
bd
2025-04-17
HALT instruction... but it voids future stages' instructions
bd
2025-04-17
Functioning PUSH/POP
bd
2025-04-17
The pipeline says some things and there are numbers
bd
2025-04-17
Keep track of checked out in DTO to simplify wb cond logic (bug)
bd
2025-04-16
Fix instruction opcode numbering issue, use assembler's output
bd
2025-04-16
Partial fixes for changes in DRAM/Cache, including uncovered bug
bd
2025-04-15
Added pipeline to GUI
Siddarth-Suresh
2025-04-02
Last fix to demo program
bd
2025-04-01
Fix bug with decode pushing checked_out when delayed with RAW
bd
2025-04-01
GUI and controller on separate threads
Siddarth-Suresh