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RISC-VECTOR.git
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A simulator for the custom RISC-V[ECTOR] ISA written in C++
bd
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dram.h
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Author
2025-04-11
Move storage to a separate git repository.
bd
2025-03-26
Add fetch stage implementation, tests, program loading, DTO object
bd
2025-03-23
Initial GUI Commit
Siddarth-Suresh
2025-03-22
Add controller.h, implementation and tests.
bd
2025-03-21
add 'process' function to handle boilerplate on every request
bd
2025-03-21
Small cleanups to up a lot of inplementation details
bd
2025-03-20
Rewrite all Dram tests to use Fixture
bd
2025-03-11
Rename read/write to read_line and write_word
bd
2025-03-11
Resolving conflicts
Siddarth-Suresh
2025-03-11
support for reading word, writing line to storage, dirty cache eviction, ↵
Siddarth-Suresh
cache load
2025-03-11
Write line, dirty cache eviction, cache load word/line (for future ↵
Siddarth-Suresh
multilevel cache implementation)
2025-03-11
fix namespace issues with match function
bd
2025-03-10
overload << operator for dram
bd
2025-03-09
Move do_write to dram.h, is_blocked flag
bd
2025-03-09
Code review comments
Siddarth-Suresh
2025-03-09
Implement dram load
Siddarth-Suresh
2025-03-08
Refactor function return scheme
bd
2025-03-06
dram write (no delay, no accessor tracking
bd
2025-03-06
Storage.view method, some initial tests
bd
2025-03-05
whitespace
bd
2025-03-05
constructors + method declarations for cache, dram, reponse, storage
bd
2025-03-04
Impartial storage/dram classes
bd
