index
:
RISC-VECTOR.git
master
A simulator for the custom RISC-V[ECTOR] ISA written in C++
bd
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
inc
/
instrDTO.h
Age
Commit message (
Collapse
)
Author
28 hours
Add I_VECT field type for SRDL, SRDS, with two vector reg 1 general
bd
44 hours
Separate ex advance into methods handling different field types
bd
46 hours
Rename load/store vector to i_vector
bd
46 hours
Add type field to InstrDTO, required for next refactor
bd
48 hours
Fix issue where decode would overwrite raw bits while in use
bd
2025-04-27
WB and MEM changes for vectors
Siddarth-Suresh
2025-04-26
Fix for load and store vector
Siddarth-Suresh
2025-04-26
Initial vector extension changes
Siddarth-Suresh
2025-04-22
Cleanup some imports
bd
2025-04-22
Remove 'type' field out of InstrDTO
bd
2025-04-22
Use a struct for InstrDTO
bd
2025-04-22
Remove the accessor object
bd
2025-04-21
Add licensing information
bd
2025-04-18
Keep track of squashed instructions in DTO object
bd
2025-04-17
Keep track of checked out in DTO to simplify wb cond logic (bug)
bd
2025-04-01
Lots of fixes and tests
bd
2025-03-31
MEM WB stage
Siddarth-Suresh
2025-03-29
Add implementation functions for checking out a register.
bd
2025-03-27
Use an unordered map to record pipe stage history on instructions
bd
2025-03-27
Instr, InstrDTO gets/sets, other structures required for decode
bd
2025-03-26
Add fetch stage implementation, tests, program loading, DTO object
bd
