index
:
RISC-VECTOR.git
master
A simulator for the custom RISC-V[ECTOR] ISA written in C++
bd
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
sim
/
controller.cc
Age
Commit message (
Collapse
)
Author
2025-04-17
Add option to turn off pipeline
bd
2025-04-17
HALT instruction... but it voids future stages' instructions
bd
2025-04-17
The pipeline says some things and there are numbers
bd
2025-04-01
Fix bug with decode pushing checked_out when delayed with RAW
bd
2025-04-01
Merge remote-tracking branch 'origin/master' into bdunahu
bd
2025-04-01
GUI and controller on separate threads
Siddarth-Suresh
2025-04-01
Lots of fixes and tests
bd
2025-04-01
Ensure all stages only do work if they are not 'OK'
bd
2025-03-31
MEM WB stage
Siddarth-Suresh
2025-03-30
Add mock stage, proper decode tests
bd
2025-03-30
Minor simplification to API between pipeline components
bd
2025-03-29
Fetch stage properly holds objects until parent is ready
bd
2025-03-29
Add parameter to Stage::advance so status can transfer down the pipe
bd
2025-03-27
Instr, InstrDTO gets/sets, other structures required for decode
bd
2025-03-26
Fix timing issues in fetch tests
bd
2025-03-26
Add fetch stage implementation, tests, program loading, DTO object
bd
2025-03-24
Add skeleton classes for 5 major pipeline stages
bd
2025-03-22
Initialize clock_cycle
bd
2025-03-22
Add controller.h, implementation and tests.
bd
