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path: root/src/sim/ex.cc
AgeCommit message (Collapse)Author
2025-04-22Remove subfoldersbd
2025-04-22Remove the accessor objectbd
2025-04-22Properly set condition codes for all operations sub SHIFTsbd
2025-04-21add RET instructionbd
2025-04-21Add licensing informationbd
2025-04-17Fix the tests which could be fixed, delete othersbd
2025-04-17HALT instruction... but it voids future stages' instructionsbd
2025-04-17Functioning PUSH/POPbd
2025-04-17The pipeline says some things and there are numbersbd
2025-04-16Partial fixes for changes in DRAM/Cache, including uncovered bugbd
2025-04-12Delete some more storage-only filesbd
2025-04-01Finish adding initial tests for full pipelinebd
2025-04-01Lots of fixes and testsbd
2025-04-01Fix a lot of pipeline bugsbd
2025-03-31Merge remote-tracking branch 'origin/dev-sid' into bdunahubd
2025-03-31Partial commit before mergebd
2025-03-31MEM WB stageSiddarth-Suresh
2025-03-30Ensure type-I instruction could use S3 as displacementbd
2025-03-30Implementation and tests for J typesbd
2025-03-30All I-type instructionsbd
2025-03-30Add tests for EXbd
2025-03-30Add mock stage, proper decode testsbd
2025-03-30untested ALU type R operationsbd
2025-03-30Setting condition code register, overflow guardbd
2025-03-30Minor simplification to API between pipeline componentsbd
2025-03-29Fetch stage properly holds objects until parent is readybd
2025-03-29Add parameter to Stage::advance so status can transfer down the pipebd
2025-03-27Instr, InstrDTO gets/sets, other structures required for decodebd
2025-03-26Add fetch stage implementation, tests, program loading, DTO objectbd
2025-03-24Add skeleton classes for 5 major pipeline stagesbd
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-13 06:36:23 +0000