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A simulator for the custom RISC-V[ECTOR] ISA written in C++
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2025-03-30
Add tests for EX
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2025-03-30
Free everything I allocated :)
bd
2025-03-30
Add mock stage, proper decode tests
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2025-03-30
untested ALU type R operations
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2025-03-30
Setting condition code register, overflow guard
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2025-03-30
Minor simplification to API between pipeline components
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2025-03-29
Quick fix to fix compile-error
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2025-03-29
Fix typo which allowed FETCH output to go to EXECUTE
bd
2025-03-29
Add advance logic for decode
bd
2025-03-29
Add tests for read/write guards
bd
2025-03-29
Add proper read and write guard methods, clean up id test file
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2025-03-29
Fetch stage properly holds objects until parent is ready
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2025-03-29
Add parameter to Stage::advance so status can transfer down the pipe
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2025-03-29
Add implementation functions for checking out a register.
bd
2025-03-29
get_instr_fields return mnemonic rather than opcode and type
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2025-03-28
Move get_instr_fields, add all instruction mnemonics
bd
2025-03-27
Use an unordered map to record pipe stage history on instructions
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2025-03-27
Instr, InstrDTO gets/sets, other structures required for decode
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2025-03-26
Fix timing issues in fetch tests
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2025-03-26
Add fetch stage implementation, tests, program loading, DTO object
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2025-03-24
Add skeleton classes for 5 major pipeline stages
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2025-03-22
Initialize clock_cycle
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2025-03-22
Add controller.h, implementation and tests.
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