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RISC-VECTOR.git
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A simulator for the custom RISC-V[ECTOR] ISA written in C++
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2025-04-01
GUI and controller on separate threads
Siddarth-Suresh
2025-04-01
Lots of fixes and tests
bd
2025-04-01
Fix a lot of pipeline bugs
bd
2025-04-01
Ensure all stages only do work if they are not 'OK'
bd
2025-03-31
Merge remote-tracking branch 'origin/dev-sid' into bdunahu
bd
2025-03-31
Partial commit before merge
bd
2025-03-31
CR Comments
Siddarth-Suresh
2025-03-31
MEM WB stage
Siddarth-Suresh
2025-03-30
Sanity check for pipeline up to exe
bd
2025-03-30
Ensure type-I instruction could use S3 as displacement
bd
2025-03-30
Implementation and tests for J types
bd
2025-03-30
All I-type instructions
bd
2025-03-30
Add tests for EX
bd
2025-03-30
Free everything I allocated :)
bd
2025-03-30
Add mock stage, proper decode tests
bd
2025-03-30
untested ALU type R operations
bd
2025-03-30
Setting condition code register, overflow guard
bd
2025-03-30
Minor simplification to API between pipeline components
bd
2025-03-29
Quick fix to fix compile-error
bd
2025-03-29
Fix typo which allowed FETCH output to go to EXECUTE
bd
2025-03-29
Add advance logic for decode
bd
2025-03-29
Add tests for read/write guards
bd
2025-03-29
Add proper read and write guard methods, clean up id test file
bd
2025-03-29
Fetch stage properly holds objects until parent is ready
bd
2025-03-29
Add parameter to Stage::advance so status can transfer down the pipe
bd
2025-03-29
Add implementation functions for checking out a register.
bd
2025-03-29
get_instr_fields return mnemonic rather than opcode and type
bd
2025-03-28
Move get_instr_fields, add all instruction mnemonics
bd
2025-03-28
add get_instr_fields func to parse instruction fields from raw bits
bd
2025-03-27
Use an unordered map to record pipe stage history on instructions
bd
2025-03-27
Instr, InstrDTO gets/sets, other structures required for decode
bd
2025-03-26
Fix timing issues in fetch tests
bd
2025-03-26
Add fetch stage implementation, tests, program loading, DTO object
bd
2025-03-25
Merge pull request #35 from bdunahu/bdunahu
Siddarth Suresh
Add skeleton classes for 5 major pipeline stages Agree with different classes for each stage
2025-03-24
Add skeleton classes for 5 major pipeline stages
bd
2025-03-24
Added gui folder with its own CMake to house GUI+main.cc
bd
2025-03-23
Remove Python, combine main files
bd
2025-03-23
Initial GUI Commit
Siddarth-Suresh
2025-03-23
Merge pull request #30 from bdunahu/bdunahu
bd
Add controller.h, implementation and tests.
2025-03-22
Remove manual clock advancing / resolution from storage devices
bd
2025-03-22
Initialize clock_cycle
bd
2025-03-22
Add controller.h, implementation and tests.
bd
2025-03-21
add 'process' function to handle boilerplate on every request
bd
2025-03-21
Small cleanups to up a lot of inplementation details
bd
2025-03-21
Rewrite current cache.cc tests, add test-helper function to dram
bd
2025-03-20
Rewrite all Dram tests to use Fixture
bd
2025-03-20
Make memory simulator an optional command, experiment with fixtures
bd
2025-03-11
Fix small issue in fetch_resource wih off by one cycle count
bd
2025-03-11
Fix issue where fetch_resource did not update cache data
bd
2025-03-11
fix lots of bugs
bd
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