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A simulator for the custom RISC-V[ECTOR] ISA written in C++
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cache.cc
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2025-04-11
Move storage to a separate git repository.
bd
2025-03-23
Merge pull request #30 from bdunahu/bdunahu
bd
Add controller.h, implementation and tests.
2025-03-22
Remove manual clock advancing / resolution from storage devices
bd
2025-03-22
Add controller.h, implementation and tests.
bd
2025-03-21
remove unused import
bd
2025-03-21
Rewrite current cache.cc tests, add test-helper function to dram
bd
2025-03-20
Rewrite all Dram tests to use Fixture
bd
2025-03-11
Merge remote-tracking branch 'origin/master' into bdunahu
bd
2025-03-11
Rename read/write to read_line and write_word
bd
2025-03-11
Clarify size of mem and cache in definitions, CLI print invalid tags
bd
2025-03-10
CLI view, clock, store, program banner
bd
2025-03-10
Update cli method signatures, add some getters to cache and storage
bd
2025-03-10
Specify memory addresses in cache tests in binary as intended
bd
2025-03-09
More cache store tests
bd
2025-03-09
Properly set cache metadata when a value is loaded
bd
2025-03-09
Cache object issues with uninitialized fields, another cache test
bd
2025-03-09
cache store single test
bd
2025-03-06
dram write (no delay, no accessor tracking
bd
2025-03-06
Storage.view method, some initial tests
bd
2025-03-05
whitespace
bd
2025-03-05
constructors + method declarations for cache, dram, reponse, storage
bd
