| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 31 hours | Replaced STOREV with LOADV | bd | |
| 2025-04-23 | Rename Response.WAIT to READY, delete BLOCKED | bd | |
| 2025-04-22 | Use a struct for InstrDTO | bd | |
| 2025-04-22 | Properly set condition codes for all operations sub SHIFTs | bd | |
| 2025-04-16 | Partial fixes for changes in DRAM/Cache, including uncovered bug | bd | |
| 2025-04-01 | Finish adding initial tests for full pipeline | bd | |
| 2025-04-01 | Ensure all stages only do work if they are not 'OK' | bd | |
| 2025-03-30 | Sanity check for pipeline up to exe | bd | |
| 2025-03-30 | Ensure type-I instruction could use S3 as displacement | bd | |
| 2025-03-30 | Implementation and tests for J types | bd | |
| 2025-03-30 | All I-type instructions | bd | |
| 2025-03-30 | Add tests for EX | bd | |
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index : RISC-VECTOR.git | |
| A simulator for the custom RISC-V[ECTOR] ISA written in C++ | bd |
| summaryrefslogtreecommitdiff |