summaryrefslogtreecommitdiff
path: root/src/sim/wb.cc
blob: 276d1d0e5659cbf42e87deb4daaf985467ed2b84 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
#include "wb.h"
#include "accessor.h"
#include "instrDTO.h"
#include "response.h"
#include "stage.h"

WB::WB(Stage *stage) : Stage(stage) { this->id = WRITE; }

void WB::advance_helper()
{
	if (this->curr_instr->get_type() == R ||
		this->curr_instr->get_type() == I) {
		if (this->checked_out.size() > 0) {
			signed int reg = this->checked_out.front();
			this->checked_out.pop_front();
			if (reg >= GPR_NUM) {
				// TODO: handle vector instructions
			} else {
				if (this->curr_instr->get_mnemonic() != STORE &&
					this->curr_instr->get_mnemonic() != STOREV) {
					this->gprs[reg] = this->curr_instr->get_s1();
				}
			}
		}
	} else if (this->curr_instr->get_type() == J) {
		// TODO:handle push pop
		// branch taken
		if (this->pc != this->curr_instr->get_s1()) {
			if (this->curr_instr->get_mnemonic() == JAL) {
				// set link register to next instruction
				this->gprs[1] = this->pc + 1;
			}
			this->pc = this->curr_instr->get_s1();
			// clear pending registers and squash pipeline
			this->checked_out = {};
			this->next->squash();
		}
	}
	this->status = OK;
}