diff options
| author | Siddarth Suresh <155843085+SiddarthSuresh98@users.noreply.github.com> | 2025-04-08 10:17:09 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-08 10:17:09 -0400 |
| commit | cc1e5892a25949b996d69a0b07f151a276ef2570 (patch) | |
| tree | 643d37db692c19d1ef64223eadcac7a28dbbd7db /README.md | |
| parent | 19d13c8339ee990fba358417a54aa6f1c94c7bca (diff) | |
| parent | b85c10ba1c53f1b442fea6bde4c2a2f73cfe5d6b (diff) | |
Merge pull request #1 from bdunahu/bdunahu
Add logic to open file, full lexer and tests.
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 25 |
1 files changed, 18 insertions, 7 deletions
@@ -1,12 +1,23 @@ -# RISC V[ECTOR] Assembler +# rva + +This is an assembler for a custom ISA nicknamed "RISC V[ECTOR]". It takes in an assembly program syntactically similar to MIPS (see input) and outputs a list of binary numbers corresponding to the instructions. The output is compatible with the [RISC V[ECTOR]](https://github.com/bdunahu/RISC-V-ECTOR-) simulator. ## Dependencies -- SBCL -- ASDF -- fiveam -- clingon +A common-lisp implementation (SBCL) and the following libraries are required to compile: + +- SBCL (tested with v2.5.2) +- ASDF (tested with v3.3.7) +- fiveam (tested with v3.3.7) +- clingon (tested with v0.5.0-1.f2a730f) +- trivia (tested with v0.1-0.8b406c3) + +## To run + +Run `make` to produce a binary file in `/bin/`. To run the unit tests, run `make test`. See the make file for further options. + +# About -## To compile +Created at the University of Massachusetts, Amherst -make +CS535 -- Computer Architecture and ISA Design
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