diff options
| author | bd <bdunahu@operationnull.com> | 2025-05-10 22:50:45 -0400 |
|---|---|---|
| committer | bd <bdunahu@operationnull.com> | 2025-05-10 22:50:45 -0400 |
| commit | 10d72fe1e3586e214353b4b942388335bc13f404 (patch) | |
| tree | b9fbdabfd6646a6b0699c604478d8ae8acaed1d7 /input | |
| parent | d1ef2e2171d660bac392c19bc0094c5e76c986f6 (diff) | |
Rename STOREV, LOADV to SRDS, SRDL
Diffstat (limited to 'input')
| -rw-r--r-- | input/adjacent-adder-vector.asm | 6 | ||||
| -rw-r--r-- | input/over_or_under.asm | 6 | ||||
| -rw-r--r-- | input/vector_fun.asm | 1 |
3 files changed, 6 insertions, 7 deletions
diff --git a/input/adjacent-adder-vector.asm b/input/adjacent-adder-vector.asm index 80bc8a3..a8fc55d 100644 --- a/input/adjacent-adder-vector.asm +++ b/input/adjacent-adder-vector.asm @@ -8,11 +8,11 @@ .text load $4 s($0) ; set the vector-length register addi $5 $0 arr - loadv $16 0($5) + srdl $16 0($5) addi $5 $5 0x1 - loadv $17 0($6) + srdl $17 0($6) addv $16 $16 $17 - storev $16 arr($0) + srds $16 arr($0) nop nop nop diff --git a/input/over_or_under.asm b/input/over_or_under.asm index 4be18ab..9ca0f05 100644 --- a/input/over_or_under.asm +++ b/input/over_or_under.asm @@ -13,9 +13,9 @@ load $4 vSiz($0) load $5 max($0) load $6 min($0) - loadv $17 max($0) - loadv $18 min($0) - loadv $19 n1($0) + srdl $17 max($0) + srdl $18 min($0) + srdl $19 n1($0) addi $7 $0 1 addi $8 $0 -1 jrl ADDROVER diff --git a/input/vector_fun.asm b/input/vector_fun.asm index eed38ce..f91b4a0 100644 --- a/input/vector_fun.asm +++ b/input/vector_fun.asm @@ -5,7 +5,6 @@ s 4 .text load $4 s($0) ; set the vector length register - LOOP: cev $17 $16 beq END |