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| author | Siddarth Suresh <155843085+SiddarthSuresh98@users.noreply.github.com> | 2025-03-26 22:05:46 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-26 22:05:46 -0400 |
| commit | 7abc8926670c1701db8011cacc9c5e2e2ca95be8 (patch) | |
| tree | fd3263d2754d662fdad6d69851f14a84f44db4d1 /src/sim/stage.cc | |
| parent | 9eeea1ab8bf4eb17e5da46d57a6c1d455a0a262e (diff) | |
| parent | 8d37d15ebd1221e3b1698abb3b051d9d0c044c93 (diff) | |
Merge pull request #36 from bdunahu/bdunahu
Add fetch stage implementation, tests, program loading, DTO object
Base classes plus base tests for Instruction Fetch stage with a default program
Diffstat (limited to 'src/sim/stage.cc')
| -rw-r--r-- | src/sim/stage.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/sim/stage.cc b/src/sim/stage.cc index 399743a..0d48774 100644 --- a/src/sim/stage.cc +++ b/src/sim/stage.cc @@ -7,3 +7,5 @@ Stage::Stage(Stage *next) { std::array<int, GPR_NUM> Stage::gprs; int Stage::pc; Storage *Stage::storage; +bool Stage::is_pipelined; +int Stage::clock_cycle; |