diff options
author | bd <bdunahu@operationnull.com> | 2025-04-17 19:56:53 -0400 |
---|---|---|
committer | bd <bdunahu@operationnull.com> | 2025-04-17 19:56:53 -0400 |
commit | 984ce6eef2e439955ff991f90c2b654be7c6c3f3 (patch) | |
tree | e936781b52c6846d87c98381ed47bc7da7c43bff /src | |
parent | 082200691a5d95f716a9d1dc127c858322cdff37 (diff) |
Add option to turn off pipeline
Diffstat (limited to 'src')
-rw-r--r-- | src/sim/controller.cc | 8 | ||||
-rw-r--r-- | src/sim/if.cc | 3 | ||||
-rw-r--r-- | src/sim/stage.cc | 1 |
3 files changed, 7 insertions, 5 deletions
diff --git a/src/sim/controller.cc b/src/sim/controller.cc index 9ae6d16..db6106c 100644 --- a/src/sim/controller.cc +++ b/src/sim/controller.cc @@ -9,6 +9,7 @@ Controller::Controller(Stage *stage, Storage *storage, bool is_pipelined) this->clock_cycle = 1; this->storage = storage; this->is_pipelined = is_pipelined; + this->is_empty = true; this->pc = 0x0; this->checked_out = {}; this->gprs = {0}; @@ -33,10 +34,6 @@ int Controller::get_clock_cycle() { return this->clock_cycle; } std::array<int, GPR_NUM> Controller::get_gprs() { return this->gprs; } -void Controller::set_gprs(int index, int value) { this->gprs[index] = value; } - -void Controller::set_pipelined(bool value) { this->is_pipelined = value; } - int Controller::get_pc() { return this->pc; } InstrDTO *Controller::advance(Response p) @@ -45,6 +42,9 @@ InstrDTO *Controller::advance(Response p) r = this->next->advance(p); ++this->clock_cycle; + if (r) + this->is_empty = true; + return r; } diff --git a/src/sim/if.cc b/src/sim/if.cc index 1223149..bab2608 100644 --- a/src/sim/if.cc +++ b/src/sim/if.cc @@ -37,13 +37,14 @@ void IF::advance_helper() int i; signed int bits; - if (this->curr_instr == nullptr) { + if (this->curr_instr == nullptr && (this->is_pipelined || this->is_empty)) { i = this->storage->read_word(this, this->pc, bits); r = i ? OK : STALLED; if (r == OK) { this->curr_instr = new InstrDTO(); this->curr_instr->set_instr_bits(bits); this->curr_instr->set_pc(this->pc); + this->is_empty = false; } } } diff --git a/src/sim/stage.cc b/src/sim/stage.cc index 7df1dba..9528e4b 100644 --- a/src/sim/stage.cc +++ b/src/sim/stage.cc @@ -17,6 +17,7 @@ std::deque<signed int> Stage::checked_out; unsigned int Stage::pc; Storage *Stage::storage; bool Stage::is_pipelined; +bool Stage::is_empty; int Stage::clock_cycle; bool Stage::get_condition(CC c) { return (this->gprs[3] >> c) & 1; } |