RISC-VECTOR.git - A simulator for the custom RISC-V[ECTOR] ISA written in C++

Age	Commit message (Expand)	Author
17 hours	Add ROTV instruction	bd
19 hours	Stride load, stride store	bd
26 hours	Add I_VECT field type for SRDL, SRDS, with two vector reg 1 general	bd
27 hours	Replaced STOREV with LOADV	bd
41 hours	Fix bug where too many vector elements were written back	bd
42 hours	Fix off-by-one in CEV equal	bd
42 hours	Fix overflow/underflow conditions in vector ops	bd
42 hours	Separate ex advance into methods handling different field types	bd
44 hours	Rename load/store vector to i_vector	bd
45 hours	Add type field to InstrDTO, required for next refactor	bd
46 hours	Fix issue where decode would overwrite raw bits while in use	bd
4 days	Move is_logical_type and is_vector_type to instr.h	bd
2025-04-27	Fix UI display to not be ridged	bd
2025-04-27	Fix push/pop instruction	bd
2025-04-27	Bug fixes	Siddarth-Suresh
2025-04-27	WB and MEM changes for vectors	Siddarth-Suresh
2025-04-27	EX changes for LOADV and STOREV	Siddarth-Suresh
2025-04-26	Initial vector extension changes	Siddarth-Suresh
2025-04-22	Use a struct for InstrDTO	bd
2025-04-22	Remove subfolders	bd