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RISC-VECTOR.git
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A simulator for the custom RISC-V[ECTOR] ISA written in C++
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ex.cc
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Author
22 hours
Add ROTV instruction
bd
24 hours
Stride load, stride store
bd
31 hours
Add I_VECT field type for SRDL, SRDS, with two vector reg 1 general
bd
31 hours
Replaced STOREV with LOADV
bd
45 hours
Fix bug where too many vector elements were written back
bd
46 hours
Fix off-by-one in CEV equal
bd
46 hours
Fix overflow/underflow conditions in vector ops
bd
47 hours
Separate ex advance into methods handling different field types
bd
2 days
Rename load/store vector to i_vector
bd
2 days
Add type field to InstrDTO, required for next refactor
bd
2 days
Fix issue where decode would overwrite raw bits while in use
bd
4 days
Move is_logical_type and is_vector_type to instr.h
bd
2025-04-27
Fix UI display to not be ridged
bd
2025-04-27
Fix push/pop instruction
bd
2025-04-27
Bug fixes
Siddarth-Suresh
2025-04-27
WB and MEM changes for vectors
Siddarth-Suresh
2025-04-27
EX changes for LOADV and STOREV
Siddarth-Suresh
2025-04-26
Initial vector extension changes
Siddarth-Suresh
2025-04-22
Use a struct for InstrDTO
bd
2025-04-22
Remove subfolders
bd
