RISC-VECTOR.git - A simulator for the custom RISC-V[ECTOR] ISA written in C++

Age	Commit message (Expand)	Author
2025-04-01	Fix bug with decode pushing checked_out when delayed with RAW	bd
2025-04-01	Finish adding initial tests for full pipeline	bd
2025-04-01	Lots of fixes and tests	bd
2025-04-01	Fix a lot of pipeline bugs	bd
2025-04-01	Ensure all stages only do work if they are not 'OK'	bd
2025-03-31	Merge remote-tracking branch 'origin/dev-sid' into bdunahu	bd
2025-03-31	Partial commit before merge	bd
2025-03-31	CR Comments	Siddarth-Suresh
2025-03-31	MEM WB stage	Siddarth-Suresh
2025-03-30	Sanity check for pipeline up to exe	bd
2025-03-30	Implementation and tests for J types	bd
2025-03-30	Add tests for EX	bd
2025-03-30	Add mock stage, proper decode tests	bd
2025-03-30	Setting condition code register, overflow guard	bd
2025-03-29	Add tests for read/write guards	bd
2025-03-29	Add proper read and write guard methods, clean up id test file	bd
2025-03-29	Fetch stage properly holds objects until parent is ready	bd
2025-03-29	Add implementation functions for checking out a register.	bd
2025-03-29	get_instr_fields return mnemonic rather than opcode and type	bd
2025-03-27	Instr, InstrDTO gets/sets, other structures required for decode	bd
2025-03-26	Add fetch stage implementation, tests, program loading, DTO object	bd
2025-03-24	Add skeleton classes for 5 major pipeline stages	bd
2025-03-22	Add controller.h, implementation and tests.	bd