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| author | bd <bdunahu@operationnull.com> | 2025-04-07 16:15:31 -0400 |
|---|---|---|
| committer | bd <bdunahu@operationnull.com> | 2025-04-07 16:15:31 -0400 |
| commit | 1ba3929b633b35a2131960b5344359478594626a (patch) | |
| tree | d14caa4848445e06c9ed40d7990607da5eb38b8b /README.md | |
| parent | 458f25364589979cd9099a9ad5fb89932511e78b (diff) | |
Update README
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 32 |
1 files changed, 25 insertions, 7 deletions
@@ -1,12 +1,30 @@ -# RISC V[ECTOR] Assembler +# rva + + _/_/ _/_/ + _/ _/ + _/ _/ _/_/ _/ _/ _/_/_/ _/ + _/ _/_/ _/ _/ _/ _/ _/ + _/ _/ _/ _/ _/ _/ _/ + _/ _/ _/ _/_/_/ _/ + _/_/ _/_/ + +This is an assembler for the custom ISA nicknamed "RISC V[ECTOR]". It takes in an assembly program syntactically similar to MIPS (see input) and outputs a list of binary numbers corresponding to the instructions. This the output is compatible with the [RISC V[ECTOR]](https://github.com/bdunahu/RISC-V-ECTOR-) simulator. ## Dependencies -- SBCL -- ASDF -- fiveam -- clingon +A common-lisp implementation (SBCL) and the following libraries are required to compile: + +- SBCL (tested with v2.5.2) +- ASDF (tested with v3.3.7) +- fiveam (tested with v3.3.7) +- clingon (tested with v0.5.0-1.f2a730f) +- trivia (tested with v0.1-0.8b406c3) + +## To run + +Run `make` to produce a binary file in `/bin/`. To run the unit tests, run `make test`. See the make file for further options. -## To compile +# About -make +Created at the University of Massachusetts, Amherst +CS535 -- Computer Architecture and ISA Design
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