diff options
| author | bd <bdunahu@operationnull.com> | 2025-05-10 22:50:45 -0400 |
|---|---|---|
| committer | bd <bdunahu@operationnull.com> | 2025-05-10 22:50:45 -0400 |
| commit | 10d72fe1e3586e214353b4b942388335bc13f404 (patch) | |
| tree | b9fbdabfd6646a6b0699c604478d8ae8acaed1d7 /input/adjacent-adder-vector.asm | |
| parent | d1ef2e2171d660bac392c19bc0094c5e76c986f6 (diff) | |
Rename STOREV, LOADV to SRDS, SRDL
Diffstat (limited to 'input/adjacent-adder-vector.asm')
| -rw-r--r-- | input/adjacent-adder-vector.asm | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/input/adjacent-adder-vector.asm b/input/adjacent-adder-vector.asm index 80bc8a3..a8fc55d 100644 --- a/input/adjacent-adder-vector.asm +++ b/input/adjacent-adder-vector.asm @@ -8,11 +8,11 @@ .text load $4 s($0) ; set the vector-length register addi $5 $0 arr - loadv $16 0($5) + srdl $16 0($5) addi $5 $5 0x1 - loadv $17 0($6) + srdl $17 0($6) addv $16 $16 $17 - storev $16 arr($0) + srds $16 arr($0) nop nop nop |