summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2025-04-12Rewrite utils functions as macrosbd
2025-04-11First part of storage rework (see description)bd
- Removed response enum. - Removed messy ostream override, and cli.cc test class - Removed accessor enum, and instead used unique pointer to identify accessor. - Simplified storage by removing is_waiting variables. - Rewrote DRAM and Cache to use Storage constructor.
2025-04-11Move source files to top-level src directorybd
2025-04-11Update namebd
2025-04-11Modify README and CMakeLists from repository splitbd
2025-04-10Update README.mdSiddarth Suresh
2025-03-30Merge pull request #41 from bdunahu/bdunahuSiddarth Suresh
Add mock stage, proper decode tests changes look good
2025-03-30Add mock stage, proper decode testsbd
2025-03-30Setting condition code register, overflow guardbd
2025-03-29Merge pull request #37 from bdunahu/bdunahuSiddarth Suresh
Instr, InstrDTO gets/sets, other structures required for decode -- tests as we move forward -- base classes -- decode stage implemented
2025-03-29Add implementation functions for checking out a register.bd
2025-03-29get_instr_fields return mnemonic rather than opcode and typebd
2025-03-28Move get_instr_fields, add all instruction mnemonicsbd
2025-03-28add get_instr_fields func to parse instruction fields from raw bitsbd
2025-03-27Instr, InstrDTO gets/sets, other structures required for decodebd
2025-03-26Merge pull request #36 from bdunahu/bdunahuSiddarth Suresh
Add fetch stage implementation, tests, program loading, DTO object Base classes plus base tests for Instruction Fetch stage with a default program
2025-03-26Add fetch stage implementation, tests, program loading, DTO objectbd
2025-03-25Merge pull request #33 from bdunahu/dev-sidSiddarth Suresh
Initial GUI Commit
2025-03-24Added gui folder with its own CMake to house GUI+main.ccbd
2025-03-23Remove Python, combine main filesbd
2025-03-23Initial GUI CommitSiddarth-Suresh
2025-03-23Merge pull request #30 from bdunahu/bdunahubd
Add controller.h, implementation and tests.
2025-03-23Merge pull request #31 from bdunahu/bdunahuerbd
Remove manual clock advancing / resolution from storage devices
2025-03-22Remove manual clock advancing / resolution from storage devicesbd
2025-03-22Add controller.h, implementation and tests.bd
2025-03-22Merge pull request #29 from bdunahu/bdunahuSiddarth Suresh
Small cleanups to up a lot of implementation details
2025-03-21Merge remote-tracking branch 'origin/master' into bdunahubd
2025-03-21Merge pull request #28 from bdunahu/bdunahuerSiddarth Suresh
Rewrite current cache.cc tests, add test-helper function to dram
2025-03-21add 'process' function to handle boilerplate on every requestbd
2025-03-21Small cleanups to up a lot of inplementation detailsbd
2025-03-21Merge remote-tracking branch 'origin/master' into bdunahuerbd
2025-03-21Merge pull request #27 from bdunahu/bdunahuSiddarth Suresh
Make memory simulator an optional command, switch to test fixtures Changes look good
2025-03-21remove unused importbd
2025-03-21Rewrite current cache.cc tests, add test-helper function to drambd
2025-03-20Rewrite all Dram tests to use Fixturebd
2025-03-20Merge remote-tracking branch 'origin/master' into bdunahubd
2025-03-20Make memory simulator an optional command, experiment with fixturesbd
2025-03-11Merge pull request #26 from bdunahu/bdunahuSiddarth Suresh
clarify macro names, implement load in CLI, fix many display issues
2025-03-11Fix small issue in fetch_resource wih off by one cycle countbd
2025-03-11Fix issue where fetch_resource did not update cache databd
2025-03-11fix lots of bugsbd
2025-03-11Call memory wrapping functions properlybd
2025-03-11clarify macro names, implement load in CLI, fix many display issuesbd
2025-03-11Merge remote-tracking branch 'origin/master' into bdunahubd
2025-03-11Merge pull request #25 from bdunahu/dev-sidbd
support for read word, write line in all levels of storage, cache load, dirty cache eviction, memory address wrapping
2025-03-11Rename read/write to read_line and write_wordbd
2025-03-11remove operation.h and branch determined by read/write in cache loadbd
2025-03-11read has to wait until cache has the right line from memory after eviction, ↵Siddarth-Suresh
write only has to wait until eviction and does not care about line replacement in cache from memory
2025-03-11Tests for write line in Dram, memory address wrapping implementation and testsSiddarth-Suresh
2025-03-11Pad memory address output with trailing zerosbd